From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2FB72C433FE for ; Wed, 16 Mar 2022 17:11:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qRrwiyhBpweB+hjwoFu7EwnKl/ri6OCq11Urs13mEaM=; b=eWe+OYjKC6MbEI xJLClFuK/a8nBZzvIzVyPUKCqmOhVmzbCpJm99cEsJSdc+wiFBos6fwBVkXFGOfol8I85xgLDOHLY EybQbEgoPTX/T0OR2Zljj0WrpHq5+xa09UfSh9M8fP8J4iknzw7eFVbPePMBIQIlac23eqs8TYNJq 9aD+hW8AbsFqJOI3sRl+9I/PTp7QQNPCzpyDfTH8D9p6bBCxH7TcqPx+WjvTfoSW0M31cRrz7eLDU 67pbRVen4lK/xzXWUU63ZQgmuqo4fnnunIccvUGzvGe9360V42uCkeXMv5kGrjsZtuJLXM34j2YEW ERWilCRNJR55WIoj5skQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUX9x-00DsHF-2Q; Wed, 16 Mar 2022 17:10:05 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUX9D-00Ds4t-Q3 for linux-arm-kernel@lists.infradead.org; Wed, 16 Mar 2022 17:09:21 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5D65661714; Wed, 16 Mar 2022 17:09:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 27329C340F5; Wed, 16 Mar 2022 17:09:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1647450558; bh=wNCL9FqpwSg8X1E6yVQpfI2eBRiEDRb81Bfd9ghyt+A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HxSl69FBh8O5slaSLsQGhNn/n1cG3vbFzyYCkhdwKWGotDK0FzUTRlE+JqIYdYXBE BU87PwbyGOhBA3bxii5qistmfdBTFnzSeOaqe0ScbRONHgM1kkul6wHM1fsD4OuqYm H9XrboP0LoeveK8c+tC0M1/gh12WSMlNaSHU7Y83aeBJZ9/nexb5z4blKX/sPjEroO foVj1hPIrvaV1MuEoprmRWW3q41u1AEgXaCRqg3q5cnuLWqLmWYCqC4erpDNrdzP+9 pB+po6WlgIetyAa4XRIdQg3dQpMeZQ9EPxqfZjFA1PrWfEhTuuoSBBL5AnTcl1+VXp Rb8VTGX/z9wAQ== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Mark Rutland , Marc Zyngier , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v2 5/9] arm64: Add sysreg header generation scripting Date: Wed, 16 Mar 2022 17:08:45 +0000 Message-Id: <20220316170849.1183941-6-broonie@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220316170849.1183941-1-broonie@kernel.org> References: <20220316170849.1183941-1-broonie@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9778; i=broonie@kernel.org; h=from:subject; bh=LEMH2mZ7ssyRvTaCEMMERvLgNwGgmLvrXVQPwqb9gl0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBiMhmaUijayr2sv282jlxFtTAMdTRpQiAVQEDdin+x 13i30mOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCYjIZmgAKCRAk1otyXVSH0N9iB/ 9KVZbooD/Ihbgl5Gp6u6dKpYZZxg1gugzwOyFZwGgNASw73mD7V/LyedWB8wl4ek7Nfr4vQ/yYx1wC NLxBYfVY7B+/Zp1rn/t29WmHbpChmrkOxwO3SMb7tWsYH4mYLjHXTPDesfOdXKFe3oRgeEWqP8ZYOI G9OaU67A3udYApu+gaZxdguB/JvzAj0IG/9FpKoWW3w08e0MyMJkncdW6JYhS/b28TZHdC0INlZSu7 poH+rrpyAfwIcWB1OD/5cTHdnsVnl8fC7KpGZTPFcKRL+dOpcrR2RFxPnsJx7n0KjCtS+eNTvbba91 8snJN1Z2uPMobhWWBZn0YUJcxQIOXA X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220316_100919_958591_37ADB5DA X-CRM114-Status: GOOD ( 30.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Mark Rutland The arm64 kernel requires some metadata for each system register it may need to access. Currently we have: * A SYS_ definition which sorresponds to a sys_reg() macro. This is used both to look up a sysreg by encoding (e.g. in KVM), and also to generate code to access a sysreg where the assembler is unaware of the specific sysreg encoding. Where assemblers support the S3__C_C_ syntax for system registers, we could use this rather than manually assembling the instructions. However, we don't have consistent definitions for these and we currently still need to handle toolchains that lack this feature. * A set of __SHIFT and __MASK definitions, which can be used to extract fields from the register, or to construct a register from a set of fields. These do not follow the convention used by , and the masks are not shifted into place, preventing their use in FIELD_PREP() and FIELD_GET(). We require the SHIFT definitions for inline assembly (and WIDTH definitions would be helpful for UBFX/SBFX), so we cannot only define a shifted MASK. Defining a SHIFT, WIDTH, shifted MASK and unshifted MASK is tedious and error-prone and life is much easier when they can be relied up to exist when writing code. * A set of __ definitions for each enumerated value a field may hold. These are used when identifying the presence of features. Atop of this, other code has to build up metadata at runtime (e.g. the sets of RES0/RES1 bits in a register). This patch adds scripting so that we can have an easier-to-manage canonical representation of this metadata, from which we can generate all the definitions necessary for various use-cases, e.g. | #define REG_ID_AA64ISAR0_EL1 S3_0_C0_C6_0 | #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) | #define SYS_ID_AA64ISAR0_EL1_Op0 3 | #define SYS_ID_AA64ISAR0_EL1_Op1 0 | #define SYS_ID_AA64ISAR0_EL1_CRn 0 | #define SYS_ID_AA64ISAR0_EL1_CRm 6 | #define SYS_ID_AA64ISAR0_EL1_Op2 0 | #define ID_AA64ISAR0_EL1_RNDR ARM64_SYSREG_BITMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_MASK ARM64_SYSREG_BITMASK(63, 60) | #define ID_AA64ISAR0_EL1_RNDR_SHIFT 60 | #define ID_AA64ISAR0_EL1_RNDR_WIDTH 4 | #define ID_AA64ISAR0_EL1_RNDR_NI ULL(0b0000) | #define ID_AA64ISAR0_EL1_RNDR_IMP ULL(0b0001) The script requires that all bits in the register be specified and that there be no overlapping fields. This helps the script spot errors in the input but means that the few registers which change layout at runtime depending on things like virtualisation settings will need some manual handling. No actual register conversions are done here but a header for the register data with some documention of the format is provided. At the moment this is only intended to express metadata from the architecture, and does not handle policy imposed by the kernel, such as values exposed to userspace or VMs. In future this could be extended to express such information. This script was mostly written by Mark Rutland but has been extended by Mark Brown to improve validation of input and better integrate with the kernel. Signed-off-by: Mark Rutland Co-Developed-by: Mark Brown Signed-off-by: Mark Brown --- arch/arm64/tools/gen-sysreg.awk | 213 ++++++++++++++++++++++++++++++++ arch/arm64/tools/sysreg | 34 +++++ 2 files changed, 247 insertions(+) create mode 100755 arch/arm64/tools/gen-sysreg.awk create mode 100644 arch/arm64/tools/sysreg diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk new file mode 100755 index 000000000000..f40cacc1eacd --- /dev/null +++ b/arch/arm64/tools/gen-sysreg.awk @@ -0,0 +1,213 @@ +#!/bin/awk -f +# SPDX-License-Identifier: GPL-2.0 +# gen-sysreg.awk: arm64 sysreg header generator +# +# Usage: awk -f gen-sysreg.awk sysregs.txt + +# Log an error and terminate +function fatal(msg) { + print "Error at " NR ": " msg > "/dev/stderr" + exit 1 +} + +# Sanity check that the start or end of a block makes sense at this point in +# the file. If not, produce an error and terminate. +# +# @this - the $Block or $EndBlock +# @prev - the only valid block to already be in (value of @block) +# @new - the new value of @block +function change_block(this, prev, new) { + if (block != prev) + fatal("unexpected " this " (inside " block ")") + + block = new +} + +# Sanity check the number of records for a field makes sense. If not, produce +# an error and terminate. +function expect_fields(nf) { + if (NF != nf) + fatal(NF " fields found where " nf " expected") +} + +# Print a CPP macro definition, padded with spaces so that the macro bodies +# line up in a column +function define(name, val) { + printf "%-48s%s\n", "#define " name, val +} + +# Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field +function define_field(reg, field, msb, lsb) { + define(reg "_" field, "ARM64_SYSREG_BITMASK(" msb ", " lsb ")") + define(reg "_" field "_MASK", "ARM64_SYSREG_BITMASK(" msb ", " lsb ")") + define(reg "_" field "_SHIFT", lsb) + define(reg "_" field "_WIDTH", msb - lsb + 1) +} + +# Parse a "[:]" string into the global variables @msb and @lsb +function parse_bitdef(reg, field, bitdef, _bits) +{ + if (bitdef ~ /^[0-9]+$/) { + msb = bitdef + lsb = bitdef + } else if (split(bitdef, _bits, ":") == 2) { + msb = _bits[1] + lsb = _bits[2] + } else { + fatal("invalid bit-range definition '" bitdef "'") + } + + + if (msb != next_bit) + fatal(reg "." field " starts at " msb " not " next_bit) + if (63 < msb || msb < 0) + fatal(reg "." field " invalid high bit in '" bitdef "'") + if (63 < lsb || lsb < 0) + fatal(reg "." field " invalid low bit in '" bitdef "'") + if (msb < lsb) + fatal(reg "." field " invalid bit-range '" bitdef "'") + if (low > high) + fatal(reg "." field " has invalid range " high "-" low) + + next_bit = lsb - 1 +} + +BEGIN { + print "#ifndef __ASM_SYSREG_GEN_H" + print "#define __ASM_SYSREG_GEN_H" + print "" + print "/* Generated file - do not edit */" + + block = "None" +} + +END { + print "#endif /* __ASM_SYSREG_GEN_H */" +} + +# skip blank lines and comment lines +/^$/ { next } +/^#/ { next } + +/^Sysreg/ { + change_block("Sysreg", "None", "Sysreg") + expect_fields(7) + + reg = $2 + op0 = $3 + op1 = $4 + crn = $5 + crm = $6 + op2 = $7 + + res0 = "UL(0)" + res1 = "UL(0)" + + define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2) + define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")") + + define("SYS_" reg "_Op0", op0) + define("SYS_" reg "_Op1", op1) + define("SYS_" reg "_CRn", crn) + define("SYS_" reg "_CRm", crm) + define("SYS_" reg "_Op2", op2) + + print "" + + next_bit = 63 + + next +} + +/^EndSysreg/ { + if (next_bit > 0) + fatal("Unspecified bits in " reg) + + change_block("EndSysreg", "Sysreg", "None") + + define(reg "_RES0", "(" res0 ")") + define(reg "_RES1", "(" res1 ")") + print "" + + reg = null + op0 = null + op1 = null + crn = null + crm = null + op2 = null + res0 = null + res1 = null + + next +} + +/^Res0/ && block = "Sysreg" { + expect_fields(2) + parse_bitdef(reg, "RES0", $2) + field = "RES0_" msb "_" lsb + + define_field(reg, field, msb, lsb) + print "" + + res0 = res0 " | " reg "_" field + + next +} + +/^Res1/ && block = "Sysreg" { + expect_fields(2) + parse_bitdef(reg, "RES1", $2) + field = "RES1_" msb "_" lsb + + define_field(reg, field, msb, lsb) + print "" + + res1 = res1 " | " reg "_" field + + next +} + +/^Field/ && block = "Sysreg" { + expect_fields(3) + field = $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb) + print "" + + next +} + +/^Enum/ { + change_block("Enum", "Sysreg", "Enum") + expect_fields(3) + field = $3 + parse_bitdef(reg, field, $2) + + define_field(reg, field, msb, lsb) + + next +} + +/^EndEnum/ { + change_block("EndEnum", "Enum", "Sysreg") + field = null + msb = null + lsb = null + print "" + next +} + +/0b[01]+/ && block = "Enum" { + expect_fields(2) + val = $1 + name = $2 + + define(reg "_" field "_" name, "ULL(" val ")") + next +} + +# Any lines not handled by previous rules are unexpected +{ + fatal("unhandled statement") +} diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg new file mode 100644 index 000000000000..3595c68b9a0b --- /dev/null +++ b/arch/arm64/tools/sysreg @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# System register metadata + +# Each System register is described by a Sysreg block: + +# Sysreg +# +# ... +# EndSysreg + +# Within a Sysreg block, each field can be described as one of: + +# Res0 [:] + +# Res1 [:] + +# Field [:] + +# Enum [:] +# +# ... +# EndEnum + +# For ID registers we adopt a few conventions for translating the +# language in the ARM into defines: +# +# NI - Not implemented +# IMP - Implemented +# +# In general it is recommended that new enumeration items be named for the +# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration +# item ACCDATA) though it may be more taseful to do something else. + -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel