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Thu, 15 Sep 2022 05:08:02 -0700 From: Amit Kumar Mahapatra To: , , CC: , , , , , , , Amit Kumar Mahapatra Subject: [PATCH v2 2/7] spi: spi-zynqmp-gqspi: Set CPOL and CPHA during hardware init Date: Thu, 15 Sep 2022 17:37:45 +0530 Message-ID: <20220915120750.1424984-3-amit.kumar-mahapatra@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915120750.1424984-1-amit.kumar-mahapatra@xilinx.com> References: <20220915120750.1424984-1-amit.kumar-mahapatra@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM3NAM02FT015:EE_|DM8PR02MB8296:EE_ X-MS-Office365-Filtering-Correlation-Id: b18b2f9e-f037-4928-2de8-08da9712f5fc X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qk2q35UbNLSN18D+psJ9qc2qw27DyFVqjQKYaBzvSs/bz4c3fj9efQ0uWdfQrgFKiw9J0vHAlXe56C0Vx62psfPv5VBaueDuKzUcuLZs2T3uFepKM2vavCAp1y7EC63smElwn9l8uNhjBZm2zClnVIXUCggbFaFfuG6j2w0ikmvj4SR/CDvmE5SOzBvjzG8RLrefX8sBwfG0gb07eQ83GXZkfkPOtFqqPP5LnLupK8jp73OuanDa9X3oKMcKk11VgSi7Ka+fsk7wXC8Fq1AenW9KqUK9zGLT3LGYyF9emBKA+y9DwjxnXT5pJ+p0kkq6m8j2NglhQy3puH6DQOKtk4Y/lPQJKa6j1O7BUKqSK2zPLouQUm+o6i5RFD9VwfzPwbjnBW7upXmUjwApedzUfgBmyHCTIgy0CyQ10VKbQGX8uIVegVcr7N2zhPuixyvYIKqR3+mzkk0/oyIsNeW1lOqNF2kjqP5coqgRcx0AX34LTC6bhw5cfC1NDbjyER7kh9HEBc+jyF9nwS3enV9Qrc4qwsef8dr+1xQrSlxdmaBqF/jBvsi02Mtjv3+T0M1JIlpckcZQ1o3QDkQJvZ5OSQuasqvgLPNQTVHbOz0EE7yzKts+wgmEuTiU1jt4YL2lRADmxzcOFMyopp9wK/6pMJKS8arNm1QRCD2nRn1QxVgcUuc831NuLRMu+H4AqkU3Y/OqOERSeI92EZ8RlHQSFg6I3gl+zrcWPry3fboQW6sm1awPGwqXLe74j4g0l5l/EHh5S3UI/IFtsmhC5T6ghOlUkk48kDMfLPnF1tjKewk= X-Forefront-Antispam-Report: CIP:149.199.62.198;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:xsj-pvapexch02.xlnx.xilinx.com;PTR:unknown-62-198.xilinx.com;CAT:NONE;SFS:(13230022)(4636009)(136003)(39860400002)(376002)(396003)(346002)(451199015)(46966006)(36840700001)(40470700004)(8676002)(36860700001)(40460700003)(336012)(5660300002)(186003)(110136005)(8936002)(7416002)(7696005)(26005)(54906003)(6666004)(107886003)(316002)(82310400005)(83380400001)(478600001)(2616005)(41300700001)(7636003)(36756003)(82740400003)(9786002)(47076005)(1076003)(356005)(426003)(2906002)(70586007)(40480700001)(4326008)(70206006)(102446001);DIR:OUT;SFP:1101; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org During every transfer GQSPI driver writes the CPOL & CPHA values to the configuration register. But the CPOL & CPHA values do not change in between multiple transfers, so moved the CPOL & CPHA initialization to hardware init so that the values are written only once. Signed-off-by: Amit Kumar Mahapatra --- drivers/spi/spi-zynqmp-gqspi.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index b07bb97cf874..6771496c1f86 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -264,7 +264,9 @@ static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr, * - Enable manual slave select * - Enable manual start * - Deselect all the chip select lines - * - Set the little endian mode of TX FIFO and + * - Set the little endian mode of TX FIFO + * - Set clock phase + * - Set clock polarity and * - Enable the QSPI controller */ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) @@ -303,10 +305,17 @@ static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) config_reg |= GQSPI_CFG_WP_HOLD_MASK; /* Clear pre-scalar by default */ config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; - /* CPHA 0 */ - config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; - /* CPOL 0 */ - config_reg &= ~GQSPI_CFG_CLK_POL_MASK; + /* Set CPHA */ + if (xqspi->ctlr->mode_bits & SPI_CPHA) + config_reg |= GQSPI_CFG_CLK_PHA_MASK; + else + config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; + /* Set CPOL */ + if (xqspi->ctlr->mode_bits & SPI_CPOL) + config_reg |= GQSPI_CFG_CLK_POL_MASK; + else + config_reg &= ~GQSPI_CFG_CLK_POL_MASK; + zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); /* Clear the TX and RX FIFO */ @@ -463,14 +472,6 @@ static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); - /* Set the QSPI clock phase and clock polarity */ - config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK); - - if (qspi->mode & SPI_CPHA) - config_reg |= GQSPI_CFG_CLK_PHA_MASK; - if (qspi->mode & SPI_CPOL) - config_reg |= GQSPI_CFG_CLK_POL_MASK; - config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT); zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); @@ -1162,6 +1163,9 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) goto clk_dis_all; } + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | + SPI_TX_DUAL | SPI_TX_QUAD; + /* QSPI controller initializations */ zynqmp_qspi_init_hw(xqspi); @@ -1188,8 +1192,6 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) ctlr->setup = zynqmp_qspi_setup_op; ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; ctlr->bits_per_word_mask = SPI_BPW_MASK(8); - ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; ctlr->dev.of_node = np; ctlr->auto_runtime_pm = true; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel