From: Li Yang <leoyang.li@nxp.com>
To: shawnguo@kernel.org, devicetree@vger.kernel.org
Cc: robh+dt@kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Li Yang <leoyang.li@nxp.com>,
Laurentiu Tudor <laurentiu.tudor@nxp.com>
Subject: [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC
Date: Thu, 15 Sep 2022 18:34:28 -0500 [thread overview]
Message-ID: <20220915233432.31660-6-leoyang.li@nxp.com> (raw)
In-Reply-To: <20220915233432.31660-1-leoyang.li@nxp.com>
These SoCs are really completely dma coherent in their entirety so add
the dma-coherent property at the soc level in the device tree and drop
the instances where it's specifically added to a few select devices.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 27033c558e3e..e406499a26b4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -273,6 +273,7 @@ soc: soc {
#size-cells = <2>;
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ dma-coherent;
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
@@ -355,7 +356,6 @@ crypto: crypto@1700000 {
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
@@ -794,7 +794,6 @@ pcie1: pcie@3400000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -834,7 +833,6 @@ pcie2: pcie@3500000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -874,7 +872,6 @@ pcie3: pcie@3600000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- dma-coherent;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
--
2.37.1
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next prev parent reply other threads:[~2022-09-15 23:36 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-15 23:34 [PATCH v2 0/9] accumulated dts updates for ls1046a Li Yang
2022-09-15 23:34 ` [PATCH v2 1/9] arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node Li Yang
2022-09-15 23:34 ` [PATCH v2 2/9] arm64: dts: ls1046a: Add the PME interrupt and big-endian to PCIe EP nodes Li Yang
2022-09-15 23:34 ` [PATCH v2 3/9] arm64: dts: ls1046a: Add big-endian property for PCIe nodes Li Yang
2022-09-15 23:34 ` [PATCH v2 4/9] arm64: dts: ls1046a: add missing dma ranges property Li Yang
2022-09-15 23:34 ` Li Yang [this message]
2022-09-23 16:10 ` [PATCH v2 5/9] arm64: dts: ls1046a: make dma-coherent global to the SoC Sean Anderson
2022-09-23 16:26 ` Leo Li
2022-09-23 16:35 ` Sean Anderson
2022-09-28 23:15 ` Leo Li
2022-09-29 15:33 ` Sean Anderson
2022-09-15 23:34 ` [PATCH v2 6/9] arm64: dts: ls1046a: use a pseudo-bus to constrain usb and sata dma size Li Yang
2022-09-15 23:34 ` [PATCH v2 7/9] arm64: dts: ls1046a: add gpios based i2c recovery information Li Yang
2022-09-15 23:34 ` [PATCH v2 8/9] arm64: dts: ls1046a-qds: add mmio based mdio-mux nodes for FPGA Li Yang
2022-09-15 23:34 ` [PATCH v2 9/9] arm64: dts: ls1046a-qds: Modify the qspi flash frequency Li Yang
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