From: Bo-Chen Chen <rex-bc.chen@mediatek.com>
To: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<matthias.bgg@gmail.com>
Cc: <angelogioacchino.delregno@collabora.com>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Bo-Chen Chen <rex-bc.chen@mediatek.com>
Subject: [PATCH v3 1/4] arm64: dts: mt8195: Add dp-intf nodes
Date: Fri, 16 Sep 2022 10:50:56 +0800 [thread overview]
Message-ID: <20220916025059.16673-2-rex-bc.chen@mediatek.com> (raw)
In-Reply-To: <20220916025059.16673-1-rex-bc.chen@mediatek.com>
Dp-intfs provide the pixel data to edptx and dptx. To support edptx
and dptx, we need to add dp-intf0 and dp-intf1 nodes.
Dp-intf0 is for edptx and dp-intf1 is for dptx.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 905d1a90b406..82d28e9f60c3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2067,6 +2067,17 @@
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
};
+ dp_intf0: dp-intf@1c015000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c015000 0 0x1000>;
+ interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys0 CLK_VDO0_DP_INTF0>,
+ <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL1>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
+
mutex: mutex@1c016000 {
compatible = "mediatek,mt8195-disp-mutex";
reg = <0 0x1c016000 0 0x1000>;
@@ -2155,5 +2166,17 @@
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
+
+ dp_intf1: dp-intf@1c113000 {
+ compatible = "mediatek,mt8195-dp-intf";
+ reg = <0 0x1c113000 0 0x1000>;
+ interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+ <&vdosys1 CLK_VDO1_DPINTF>,
+ <&apmixedsys CLK_APMIXED_TVDPLL2>;
+ clock-names = "engine", "pixel", "pll";
+ status = "disabled";
+ };
};
};
--
2.18.0
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next prev parent reply other threads:[~2022-09-16 3:48 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-16 2:50 [PATCH v3 0/4] Add dp-intf and dp nodes Bo-Chen Chen
2022-09-16 2:50 ` Bo-Chen Chen [this message]
2022-09-16 2:50 ` [PATCH v3 2/4] arm64: dts: mt8195: Add edptx and dptx nodes Bo-Chen Chen
2022-09-16 2:50 ` [PATCH v3 3/4] arm64: dts: mediatek: cherry: Add dp-intf ports Bo-Chen Chen
2022-09-16 2:50 ` [PATCH v3 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support Bo-Chen Chen
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