From: Chunfeng Yun <chunfeng.yun@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>, Vinod Koul <vkoul@kernel.org>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
"Matthias Brugger" <matthias.bgg@gmail.com>,
<dri-devel@lists.freedesktop.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-phy@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
Jitao Shi <jitao.shi@mediatek.com>,
Stanley Chu <stanley.chu@mediatek.com>
Subject: [PATCH 10/18] phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field
Date: Tue, 20 Sep 2022 17:00:30 +0800 [thread overview]
Message-ID: <20220920090038.15133-11-chunfeng.yun@mediatek.com> (raw)
In-Reply-To: <20220920090038.15133-1-chunfeng.yun@mediatek.com>
Use FIELD_PREP() macro to prepare bits field value, then no need define
macros of bits offset.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 70 ++++++++--------------
1 file changed, 26 insertions(+), 44 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
index 55fe97f5465d..8f93991fb09d 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
@@ -9,27 +9,17 @@
#define HDMI_CON0 0x00
#define RG_HDMITX_PLL_EN BIT(31)
#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)
-#define PLL_FBKDIV_SHIFT 24
#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)
-#define PLL_FBKSEL_SHIFT 22
#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)
-#define PREDIV_SHIFT 20
#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)
-#define POSDIV_SHIFT 18
#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)
#define RG_HDMITX_PLL_IR GENMASK(15, 12)
-#define PLL_IR_SHIFT 12
#define RG_HDMITX_PLL_IC GENMASK(11, 8)
-#define PLL_IC_SHIFT 8
#define RG_HDMITX_PLL_BP GENMASK(7, 4)
-#define PLL_BP_SHIFT 4
#define RG_HDMITX_PLL_BR GENMASK(3, 2)
-#define PLL_BR_SHIFT 2
#define RG_HDMITX_PLL_BC GENMASK(1, 0)
-#define PLL_BC_SHIFT 0
#define HDMI_CON1 0x04
#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)
-#define PLL_DIVEN_SHIFT 29
#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)
#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)
@@ -40,7 +30,6 @@
#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)
-#define PLL_TXDIV_SHIFT 10
#define RG_HDMITX_PLL_LVROD_EN BIT(9)
#define RG_HDMITX_PLL_MONVC_EN BIT(8)
#define RG_HDMITX_PLL_MONCK_EN BIT(7)
@@ -58,7 +47,6 @@
#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)
#define RG_HDMITX_DRV_EN GENMASK(19, 16)
#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)
-#define DRV_IMP_EN_SHIFT 12
#define RG_HDMITX_MHLCK_FORCE BIT(10)
#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
#define RG_HDMITX_MHLCK_EN BIT(8)
@@ -72,28 +60,16 @@
#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)
#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)
#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)
-#define PRD_IBIAS_CLK_SHIFT 24
-#define PRD_IBIAS_D2_SHIFT 16
-#define PRD_IBIAS_D1_SHIFT 8
-#define PRD_IBIAS_D0_SHIFT 0
#define HDMI_CON5 0x14
#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)
#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)
#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)
#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)
-#define DRV_IBIAS_CLK_SHIFT 24
-#define DRV_IBIAS_D2_SHIFT 16
-#define DRV_IBIAS_D1_SHIFT 8
-#define DRV_IBIAS_D0_SHIFT 0
#define HDMI_CON6 0x18
#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)
#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)
#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)
#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)
-#define DRV_IMP_CLK_SHIFT 24
-#define DRV_IMP_D2_SHIFT 16
-#define DRV_IMP_D1_SHIFT 8
-#define DRV_IMP_D0_SHIFT 0
#define HDMI_CON7 0x1c
#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)
#define RG_HDMITX_SER_DIN GENMASK(25, 16)
@@ -178,21 +154,27 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
}
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
+ FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div),
+ RG_HDMITX_PLL_PREDIV);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
+ FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
+ FIELD_PREP(RG_HDMITX_PLL_IR, 0x1),
RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
- (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
+ FIELD_PREP(RG_HDMITX_PLL_TXDIV, div),
+ RG_HDMITX_PLL_TXDIV);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
+ FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
+ FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19),
RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
- (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
+ FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2),
+ RG_HDMITX_PLL_DIVEN);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
- (0x1 << PLL_BR_SHIFT),
+ FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
+ FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
+ FIELD_PREP(RG_HDMITX_PLL_BR, 0x1),
RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
RG_HDMITX_PLL_BR);
if (rate < 165000000) {
@@ -209,29 +191,29 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
hdmi_ibias = hdmi_phy->ibias_up;
}
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
- (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
- (pre_ibias << PRD_IBIAS_D2_SHIFT) |
- (pre_ibias << PRD_IBIAS_D1_SHIFT) |
- (pre_ibias << PRD_IBIAS_D0_SHIFT),
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias),
RG_HDMITX_PRD_IBIAS_CLK |
RG_HDMITX_PRD_IBIAS_D2 |
RG_HDMITX_PRD_IBIAS_D1 |
RG_HDMITX_PRD_IBIAS_D0);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
- (imp_en << DRV_IMP_EN_SHIFT),
+ FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en),
RG_HDMITX_DRV_IMP_EN);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
- (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
- (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
- (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
- (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
+ FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
+ FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
+ FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
+ FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0),
RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
- (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
- (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
- (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
- (hdmi_ibias << DRV_IBIAS_D0_SHIFT),
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias),
RG_HDMITX_DRV_IBIAS_CLK |
RG_HDMITX_DRV_IBIAS_D2 |
RG_HDMITX_DRV_IBIAS_D1 |
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-20 9:07 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
2022-09-20 9:00 ` [PATCH 01/18] phy: mediatek: add a new helper to update bitfield Chunfeng Yun
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-22 2:36 ` Chunfeng Yun
2022-09-22 7:17 ` AngeloGioacchino Del Regno
2022-09-23 6:03 ` Chunfeng Yun
2022-09-20 9:00 ` [PATCH 02/18] phy: mediatek: tphy: remove macros to prepare bitfield value Chunfeng Yun
2022-09-20 9:00 ` [PATCH 03/18] phy: mediatek: xsphy: remove macros used " Chunfeng Yun
2022-09-20 9:00 ` [PATCH 04/18] phy: mediatek: ufs: use common register access helpers Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 05/18] phy: mediatek: pcie: use new helper to update register bits Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 06/18] phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 07/18] phy: mediatek: hdmi: mt2701: use FIELD_PREP to prepare bits field Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 08/18] phy: mediatek: hdmi: mt2701: use common helper to access registers Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 09/18] phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` Chunfeng Yun [this message]
2022-09-21 8:13 ` [PATCH 10/18] phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 11/18] phy: mediatek: hdmi: mt8173: use common helper to access registers Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 12/18] phy: mediatek: hdmi: remove register access helpers Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 14/18] phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 15/18] phy: mediatek: mipi: mt8173: use common helper to access registers Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 16/18] phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 17/18] phy: mediatek: mipi: mt8183: use common helper to access registers Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 18/18] phy: mediatek: mipi: remove register access helpers Chunfeng Yun
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-24 6:28 ` [PATCH 00/18] unify register access and macros Vinod Koul
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