Re: [PATCH v2 1/4] gpio: mvebu: Fix check for pwm support on non-A8K platforms

From: "Pali Rohár" <pali@kernel.org>
To: "Thierry Reding" <thierry.reding@gmail.com>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Lee Jones" <lee.jones@linaro.org>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Bartosz Golaszewski" <brgl@bgdev.pl>,
	"Rob Herring" <robh+dt@kernel.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Andrew Lunn" <andrew@lunn.ch>,
	"Gregory Clement" <gregory.clement@bootlin.com>,
	"Sebastian Hesselbarth" <sebastian.hesselbarth@gmail.com>,
	"Marek Behún" <kabel@kernel.org>
Cc: linux-pwm@vger.kernel.org, linux-gpio@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/4] gpio: mvebu: Fix check for pwm support on non-A8K platforms
Date: Sat, 24 Sep 2022 12:34:37 +0200	[thread overview]
Message-ID: <20220924103437.ww4urmq6cnhzj373@pali> (raw)
In-Reply-To: <20220714183328.4137-1-pali@kernel.org>

PING?

On Thursday 14 July 2022 20:33:25 Pali Rohár wrote:
> pwm support incompatible with Armada 80x0/70x0 API is not only in
> Armada 370, but also in Armada XP, 38x and 39x. So basically every non-A8K
> platform. Fix check for pwm support appropriately.
> 
> Fixes: 85b7d8abfec7 ("gpio: mvebu: add pwm support for Armada 8K/7K")
> Signed-off-by: Pali Rohár <pali@kernel.org>
> 
> ---
> Changes in v2:
> * reverse the if/else order per Baruch request
> ---
>  drivers/gpio/gpio-mvebu.c | 15 ++++++---------
>  1 file changed, 6 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
> index 2db19cd640a4..de1e7a1a76f2 100644
> --- a/drivers/gpio/gpio-mvebu.c
> +++ b/drivers/gpio/gpio-mvebu.c
> @@ -793,8 +793,12 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
>  	u32 offset;
>  	u32 set;
>  
> -	if (of_device_is_compatible(mvchip->chip.of_node,
> -				    "marvell,armada-370-gpio")) {
> +	if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
> +		int ret = of_property_read_u32(dev->of_node,
> +					       "marvell,pwm-offset", &offset);
> +		if (ret < 0)
> +			return 0;
> +	} else {
>  		/*
>  		 * There are only two sets of PWM configuration registers for
>  		 * all the GPIO lines on those SoCs which this driver reserves
> @@ -804,13 +808,6 @@ static int mvebu_pwm_probe(struct platform_device *pdev,
>  		if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"))
>  			return 0;
>  		offset = 0;
> -	} else if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) {
> -		int ret = of_property_read_u32(dev->of_node,
> -					       "marvell,pwm-offset", &offset);
> -		if (ret < 0)
> -			return 0;
> -	} else {
> -		return 0;
>  	}
>  
>  	if (IS_ERR(mvchip->clk))
> -- 
> 2.20.1
> 

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