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From: James Morse <james.morse@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Mark Brown <broonie@kernel.org>, james.morse@arm.com
Subject: [RFC PATCH 16/38] arm64/sysreg: Extend the maximum width of a register and symbole name
Date: Fri, 30 Sep 2022 15:01:49 +0100	[thread overview]
Message-ID: <20220930140211.3215348-17-james.morse@arm.com> (raw)
In-Reply-To: <20220930140211.3215348-1-james.morse@arm.com>

32bit has multiple values for its id registers, as extra properties
were added to the CPUs. Some of these end up having long names, which
exceed the fixed 48 character column that the sysreg awk script generates.

For example, the ID_MMFR1_EL1.L1Hvd field has an encoding whose natural
name would be 'invalidate Iside only'. Using this causes compile errors
as the script generates the following:
 #define ID_MMFR1_EL1_L1Hvd_INVALIDATE_ISIDE_ONLYUL(0b0001)

Add a few extra characters.

Signed-off-by: James Morse <james.morse@arm.com>
---
 arch/arm64/tools/gen-sysreg.awk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index db461921d256..c350164a3955 100755
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -33,7 +33,7 @@ function expect_fields(nf) {
 # Print a CPP macro definition, padded with spaces so that the macro bodies
 # line up in a column
 function define(name, val) {
-	printf "%-48s%s\n", "#define " name, val
+	printf "%-56s%s\n", "#define " name, val
 }
 
 # Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field
-- 
2.30.2


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  parent reply	other threads:[~2022-09-30 14:11 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-30 14:01 [RFC PATCH 00/38] arm64/sysreg: Convert aarch32 id regs James Morse
2022-09-30 14:01 ` [RFC PATCH 01/38] arm64/sysreg: Standardise naming for ID_MMFR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 02/38] arm64/sysreg: Standardise naming for ID_MMFR4_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 03/38] arm64/sysreg: Standardise naming for ID_MMFR5_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 04/38] arm64/sysreg: Standardise naming for ID_ISAR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 05/38] arm64/sysreg: Standardise naming for ID_ISAR4_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 06/38] arm64/sysreg: Standardise naming for ID_ISAR5_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 07/38] arm64/sysreg: Standardise naming for ID_ISAR6_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 08/38] arm64/sysreg: Standardise naming for ID_PFR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 09/38] arm64/sysreg: Standardise naming for ID_PFR1_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 10/38] arm64/sysreg: Standardise naming for ID_PFR2_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 11/38] arm64/sysreg: Standardise naming for ID_DFR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 12/38] arm64/sysreg: Standardise naming for ID_DFR1_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 13/38] arm64/sysreg: Standardise naming for MVFR0_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 14/38] arm64/sysreg: Standardise naming for MVFR1_EL1 James Morse
2022-09-30 14:01 ` [RFC PATCH 15/38] arm64/sysreg: Standardise naming for MVFR2_EL1 James Morse
2022-09-30 14:01 ` James Morse [this message]
2022-10-03 15:30   ` [RFC PATCH 16/38] arm64/sysreg: Extend the maximum width of a register and symbole name Mark Brown
2022-09-30 14:01 ` [RFC PATCH 17/38] arm64/sysreg: Convert ID_MMFR0_EL1 to automatic generation James Morse
2022-10-03 15:34   ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 18/38] arm64/sysreg: Convert ID_MMFR1_EL1 " James Morse
2022-10-03 15:37   ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 19/38] arm64/sysreg: Convert ID_MMFR2_EL1 " James Morse
2022-10-03 15:43   ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 20/38] arm64/sysreg: Convert ID_MMFR3_EL1 " James Morse
2022-10-03 15:46   ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 21/38] arm64/sysreg: Convert ID_MMFR4_EL1 " James Morse
2022-10-03 15:48   ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 22/38] arm64/sysreg: Convert ID_ISAR0_EL1 " James Morse
2022-10-03 15:51   ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 23/38] arm64/sysreg: Convert ID_ISAR1_EL1 " James Morse
2022-10-03 15:53   ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 24/38] arm64/sysreg: Convert ID_ISAR2_EL1 " James Morse
2022-10-03 15:58   ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 25/38] arm64/sysreg: Convert ID_ISAR3_EL1 " James Morse
2022-10-03 16:04   ` Mark Brown
2022-09-30 14:01 ` [RFC PATCH 26/38] arm64/sysreg: Convert ID_ISAR4_EL1 " James Morse
2022-10-03 16:07   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 27/38] arm64/sysreg: Convert ID_ISAR5_EL1 " James Morse
2022-10-03 16:10   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 28/38] arm64/sysreg: Convert ID_ISAR6_EL1 " James Morse
2022-10-03 16:11   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 29/38] arm64/sysreg: Convert ID_PFR0_EL1 " James Morse
2022-10-03 16:14   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 30/38] arm64/sysreg: Convert ID_PFR1_EL1 " James Morse
2022-10-03 16:16   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 31/38] arm64/sysreg: Convert ID_PFR2_EL1 " James Morse
2022-10-03 16:17   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 32/38] arm64/sysreg: Convert MVFR0_EL1 " James Morse
2022-10-03 16:19   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 33/38] arm64/sysreg: Convert MVFR1_EL1 " James Morse
2022-10-03 16:21   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 34/38] arm64/sysreg: Convert MVFR2_EL1 " James Morse
2022-10-03 16:25   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 35/38] arm64/sysreg: Convert ID_MMFR5_EL1 " James Morse
2022-10-03 16:27   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 36/38] arm64/sysreg: Convert ID_AFR0_EL1 " James Morse
2022-10-03 16:28   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 37/38] arm64/sysreg: Convert ID_DFR0_EL1 " James Morse
2022-10-03 16:30   ` Mark Brown
2022-09-30 14:02 ` [RFC PATCH 38/38] arm64/sysreg: Convert ID_DFR1_EL1 " James Morse
2022-10-03 16:32   ` Mark Brown

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