* [PATCH v2 0/3] iommu/mediatek: Add mt8365 iommu support
@ 2022-10-04 10:01 Alexandre Mergnat
2022-10-04 10:01 ` [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Alexandre Mergnat @ 2022-10-04 10:01 UTC (permalink / raw)
To: Rob Herring, Yong Wu, Matthias Brugger, Will Deacon,
Joerg Roedel, Robin Murphy, Krzysztof Kozlowski
Cc: Alexandre Mergnat, linux-kernel, linux-mediatek,
linux-arm-kernel, Fabien Parent, Markus Schneider-Pargmann,
Amjad Ouled-Ameur, devicetree, iommu
Hi,
This series contains patches related to the support of mt8365 iommu.
Thanks for your feedback so far.
Regards,
Alex
Changes in v2:
- Rebase.
- Change M4U_PORT_APU_READ & M4U_PORT_APU_WRITE port to avoid display
conflict in larb0. These definitions are used for vpu0 device node.
- Add dual license.
- Retitle commit.
- Rename to int_id_port_width for more detail.
- Fix typo.
- Set banks_enable and banks_num in mt8365_data to fix kernel panic at boot.
Previous versions:
v1 - https://lore.kernel.org/lkml/20220530180328.845692-1-fparent@baylibre.com/
To: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>
To: Will Deacon <will@kernel.org>
To: Robin Murphy <robin.murphy@arm.com>
To: Rob Herring <robh+dt@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
To: Matthias Brugger <matthias.bgg@gmail.com>
Cc: iommu@lists.linux.dev
Cc: linux-mediatek@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Fabien Parent <fparent@baylibre.com>
Cc: Markus Schneider-Pargmann <msp@baylibre.com>
Cc: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
Fabien Parent (3):
dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
iommu/mediatek: add support for 6-bit encoded port IDs
iommu/mediatek: add support for MT8365 SoC
.../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
drivers/iommu/mtk_iommu.c | 38 ++++++++-
include/dt-bindings/memory/mt8365-larb-port.h | 90 ++++++++++++++++++++++
3 files changed, 126 insertions(+), 4 deletions(-)
---
base-commit: 11082343e3bf2953a937509f0316cabf69dbf908
change-id: 20221001-iommu-support-f409c7e094e6
Best regards,
--
Alexandre Mergnat <amergnat@baylibre.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
2022-10-04 10:01 [PATCH v2 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
@ 2022-10-04 10:01 ` Alexandre Mergnat
2022-10-04 12:01 ` AngeloGioacchino Del Regno
2022-10-06 9:29 ` Markus Schneider-Pargmann
2022-10-04 10:01 ` [PATCH v2 2/3] iommu/mediatek: add support for 6-bit encoded port IDs Alexandre Mergnat
2022-10-04 10:01 ` [PATCH v2 3/3] iommu/mediatek: add support for MT8365 SoC Alexandre Mergnat
2 siblings, 2 replies; 9+ messages in thread
From: Alexandre Mergnat @ 2022-10-04 10:01 UTC (permalink / raw)
To: Rob Herring, Yong Wu, Matthias Brugger, Will Deacon,
Joerg Roedel, Robin Murphy, Krzysztof Kozlowski
Cc: Alexandre Mergnat, linux-kernel, linux-mediatek,
linux-arm-kernel, Fabien Parent, Markus Schneider-Pargmann,
Amjad Ouled-Ameur, devicetree, iommu
From: Fabien Parent <fparent@baylibre.com>
Add IOMMU binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
.../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
include/dt-bindings/memory/mt8365-larb-port.h | 90 ++++++++++++++++++++++
2 files changed, 92 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index fee0241b5098..4b8cf3ce6963 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -81,6 +81,7 @@ properties:
- mediatek,mt8195-iommu-vdo # generation two
- mediatek,mt8195-iommu-vpp # generation two
- mediatek,mt8195-iommu-infra # generation two
+ - mediatek,mt8365-m4u # generation two
- description: mt7623 generation one
items:
@@ -130,6 +131,7 @@ properties:
dt-binding/memory/mt8186-memory-port.h for mt8186,
dt-binding/memory/mt8192-larb-port.h for mt8192.
dt-binding/memory/mt8195-memory-port.h for mt8195.
+ dt-binding/memory/mt8365-larb-port.h for mt8365.
power-domains:
maxItems: 1
diff --git a/include/dt-bindings/memory/mt8365-larb-port.h b/include/dt-bindings/memory/mt8365-larb-port.h
new file mode 100644
index 000000000000..56d5a5dd519e
--- /dev/null
+++ b/include/dt-bindings/memory/mt8365-larb-port.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
+
+#include <dt-bindings/memory/mtk-memory-port.h>
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8)
+#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9)
+#define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10)
+#define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11)
+
+/* larb1 */
+#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB1_ID, 9)
+#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 10)
+#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB1_ID, 11)
+#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 12)
+#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB1_ID, 13)
+#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 14)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 15)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 16)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 17)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 18)
+
+/* larb2 */
+#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2)
+#define M4U_PORT_CAM_LCS MTK_M4U_ID(M4U_LARB2_ID, 3)
+#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4)
+#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(M4U_LARB2_ID, 5)
+#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(M4U_LARB2_ID, 6)
+#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 7)
+#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 8)
+#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB2_ID, 9)
+#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB2_ID, 10)
+#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 11)
+#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 12)
+#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 13)
+#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 14)
+#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 15)
+#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 16)
+#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(M4U_LARB2_ID, 17)
+#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(M4U_LARB2_ID, 18)
+#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(M4U_LARB2_ID, 19)
+#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(M4U_LARB2_ID, 20)
+#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(M4U_LARB2_ID, 21)
+#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(M4U_LARB2_ID, 22)
+#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(M4U_LARB2_ID, 23)
+
+/* larb3 */
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB3_ID, 8)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB3_ID, 9)
+#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10)
+
+#endif
--
b4 0.10.1
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/3] iommu/mediatek: add support for 6-bit encoded port IDs
2022-10-04 10:01 [PATCH v2 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
2022-10-04 10:01 ` [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
@ 2022-10-04 10:01 ` Alexandre Mergnat
2022-10-04 11:59 ` AngeloGioacchino Del Regno
2022-10-04 10:01 ` [PATCH v2 3/3] iommu/mediatek: add support for MT8365 SoC Alexandre Mergnat
2 siblings, 1 reply; 9+ messages in thread
From: Alexandre Mergnat @ 2022-10-04 10:01 UTC (permalink / raw)
To: Rob Herring, Yong Wu, Matthias Brugger, Will Deacon,
Joerg Roedel, Robin Murphy, Krzysztof Kozlowski
Cc: Alexandre Mergnat, linux-kernel, linux-mediatek,
linux-arm-kernel, Fabien Parent, Markus Schneider-Pargmann,
Amjad Ouled-Ameur, devicetree, iommu
From: Fabien Parent <fparent@baylibre.com>
Until now the port ID was always encoded as a 5-bit data. On MT8365,
the port ID is encoded as a 6-bit data. This requires to rework the
macros F_MMU_INT_ID_LARB_ID, and F_MMU_INT_ID_PORT_ID in order
to support 5-bit and 6-bit encoded port IDs.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
drivers/iommu/mtk_iommu.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5a4e00e4bbbc..a57ce509c8b5 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -108,8 +108,10 @@
#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
#define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
#define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
-#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
-#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
+#define F_MMU_INT_ID_LARB_ID(a, int_id_port_width) \
+ ((a) >> (((int_id_port_width) + 2) & 0x7))
+#define F_MMU_INT_ID_PORT_ID(a, int_id_port_width) \
+ (((a) >> 2) & GENMASK((int_id_port_width) - 1, 0))
#define MTK_PROTECT_PA_ALIGN 256
#define MTK_IOMMU_BANK_SZ 0x1000
@@ -188,6 +190,7 @@ struct mtk_iommu_plat_data {
enum mtk_iommu_plat m4u_plat;
u32 flags;
u32 inv_sel_reg;
+ u8 int_id_port_width;
char *pericfg_comp_str;
struct list_head *hw_list;
@@ -441,7 +444,8 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_pa |= (u64)pa34_32 << 32;
if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
- fault_port = F_MMU_INT_ID_PORT_ID(regval);
+ fault_port = F_MMU_INT_ID_PORT_ID(regval,
+ data->plat_data->int_id_port_width);
if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
fault_larb = F_MMU_INT_ID_COMM_ID(regval);
sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
@@ -449,7 +453,8 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
} else {
- fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+ fault_larb = F_MMU_INT_ID_LARB_ID(
+ regval, data->plat_data->int_id_port_width);
}
fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
}
@@ -1379,6 +1384,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
.banks_enable = {true},
.iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}, {6}, {7}},
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt6779_data = {
@@ -1391,6 +1397,7 @@ static const struct mtk_iommu_plat_data mt6779_data = {
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}},
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt6795_data = {
@@ -1404,6 +1411,7 @@ static const struct mtk_iommu_plat_data mt6795_data = {
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt8167_data = {
@@ -1415,6 +1423,7 @@ static const struct mtk_iommu_plat_data mt8167_data = {
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {1}, {2}}, /* Linear mapping. */
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt8173_data = {
@@ -1428,6 +1437,7 @@ static const struct mtk_iommu_plat_data mt8173_data = {
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt8183_data = {
@@ -1439,6 +1449,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),
.larbid_remap = {{0}, {4}, {5}, {6}, {7}, {2}, {3}, {1}},
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt8186_data_mm = {
@@ -1453,6 +1464,7 @@ static const struct mtk_iommu_plat_data mt8186_data_mm = {
.banks_enable = {true},
.iova_region = mt8192_multi_dom,
.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt8192_data = {
@@ -1466,6 +1478,7 @@ static const struct mtk_iommu_plat_data mt8192_data = {
.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
.larbid_remap = {{0}, {1}, {4, 5}, {7}, {2}, {9, 11, 19, 20},
{0, 14, 16}, {0, 13, 18, 17}},
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt8195_data_infra = {
@@ -1481,6 +1494,7 @@ static const struct mtk_iommu_plat_data mt8195_data_infra = {
},
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt8195_data_vdo = {
@@ -1495,6 +1509,7 @@ static const struct mtk_iommu_plat_data mt8195_data_vdo = {
.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
.larbid_remap = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
{13, 17, 15/* 17b */, 25}, {5}},
+ .int_id_port_width = 5,
};
static const struct mtk_iommu_plat_data mt8195_data_vpp = {
@@ -1513,6 +1528,7 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = {
/* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
{14, 16, 29, 26, 30, 31, 18},
{4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
+ .int_id_port_width = 5,
};
static const struct of_device_id mtk_iommu_of_ids[] = {
--
b4 0.10.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/3] iommu/mediatek: add support for MT8365 SoC
2022-10-04 10:01 [PATCH v2 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
2022-10-04 10:01 ` [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
2022-10-04 10:01 ` [PATCH v2 2/3] iommu/mediatek: add support for 6-bit encoded port IDs Alexandre Mergnat
@ 2022-10-04 10:01 ` Alexandre Mergnat
2022-10-04 12:00 ` AngeloGioacchino Del Regno
2 siblings, 1 reply; 9+ messages in thread
From: Alexandre Mergnat @ 2022-10-04 10:01 UTC (permalink / raw)
To: Rob Herring, Yong Wu, Matthias Brugger, Will Deacon,
Joerg Roedel, Robin Murphy, Krzysztof Kozlowski
Cc: Alexandre Mergnat, linux-kernel, linux-mediatek,
linux-arm-kernel, Fabien Parent, Markus Schneider-Pargmann,
Amjad Ouled-Ameur, devicetree, iommu
From: Fabien Parent <fparent@baylibre.com>
Add IOMMU support for MT8365 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Tested-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
---
drivers/iommu/mtk_iommu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index a57ce509c8b5..ce8c9660208e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -167,6 +167,7 @@ enum mtk_iommu_plat {
M4U_MT8186,
M4U_MT8192,
M4U_MT8195,
+ M4U_MT8365,
};
struct mtk_iommu_iova_region {
@@ -1531,6 +1532,18 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = {
.int_id_port_width = 5,
};
+static const struct mtk_iommu_plat_data mt8365_data = {
+ .m4u_plat = M4U_MT8365,
+ .flags = RESET_AXI,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .banks_num = 1,
+ .banks_enable = {true},
+ .iova_region = single_domain,
+ .iova_region_nr = ARRAY_SIZE(single_domain),
+ .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
+ .int_id_port_width = 6,
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
@@ -1543,6 +1556,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
{ .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
{ .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
+ { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
{}
};
--
b4 0.10.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/3] iommu/mediatek: add support for 6-bit encoded port IDs
2022-10-04 10:01 ` [PATCH v2 2/3] iommu/mediatek: add support for 6-bit encoded port IDs Alexandre Mergnat
@ 2022-10-04 11:59 ` AngeloGioacchino Del Regno
2022-10-06 10:46 ` Robin Murphy
0 siblings, 1 reply; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-10-04 11:59 UTC (permalink / raw)
To: Alexandre Mergnat, Rob Herring, Yong Wu, Matthias Brugger,
Will Deacon, Joerg Roedel, Robin Murphy, Krzysztof Kozlowski
Cc: linux-kernel, linux-mediatek, linux-arm-kernel, Fabien Parent,
Markus Schneider-Pargmann, Amjad Ouled-Ameur, devicetree, iommu
Il 04/10/22 12:01, Alexandre Mergnat ha scritto:
> From: Fabien Parent <fparent@baylibre.com>
>
> Until now the port ID was always encoded as a 5-bit data. On MT8365,
> the port ID is encoded as a 6-bit data. This requires to rework the
> macros F_MMU_INT_ID_LARB_ID, and F_MMU_INT_ID_PORT_ID in order
> to support 5-bit and 6-bit encoded port IDs.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
> drivers/iommu/mtk_iommu.c | 24 ++++++++++++++++++++----
> 1 file changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 5a4e00e4bbbc..a57ce509c8b5 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -108,8 +108,10 @@
> #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
> #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
> #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
> -#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
> -#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
> +#define F_MMU_INT_ID_LARB_ID(a, int_id_port_width) \
> + ((a) >> (((int_id_port_width) + 2) & 0x7))
> +#define F_MMU_INT_ID_PORT_ID(a, int_id_port_width) \
> + (((a) >> 2) & GENMASK((int_id_port_width) - 1, 0))
I can't think about any cleaner way than this one, but that's decreasing human
readability by "quite a bit".
The only way you can keep it readable is by adding a comment before these macros
that explains the sub-fields of FAULT_ID, located in the INT_ID register: please
add that.
Regards,
Angelo
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 3/3] iommu/mediatek: add support for MT8365 SoC
2022-10-04 10:01 ` [PATCH v2 3/3] iommu/mediatek: add support for MT8365 SoC Alexandre Mergnat
@ 2022-10-04 12:00 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-10-04 12:00 UTC (permalink / raw)
To: Alexandre Mergnat, Rob Herring, Yong Wu, Matthias Brugger,
Will Deacon, Joerg Roedel, Robin Murphy, Krzysztof Kozlowski
Cc: linux-kernel, linux-mediatek, linux-arm-kernel, Fabien Parent,
Markus Schneider-Pargmann, Amjad Ouled-Ameur, devicetree, iommu
Il 04/10/22 12:01, Alexandre Mergnat ha scritto:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add IOMMU support for MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Reviewed-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
> Tested-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
2022-10-04 10:01 ` [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
@ 2022-10-04 12:01 ` AngeloGioacchino Del Regno
2022-10-06 9:29 ` Markus Schneider-Pargmann
1 sibling, 0 replies; 9+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-10-04 12:01 UTC (permalink / raw)
To: Alexandre Mergnat, Rob Herring, Yong Wu, Matthias Brugger,
Will Deacon, Joerg Roedel, Robin Murphy, Krzysztof Kozlowski
Cc: linux-kernel, linux-mediatek, linux-arm-kernel, Fabien Parent,
Markus Schneider-Pargmann, Amjad Ouled-Ameur, devicetree, iommu
Il 04/10/22 12:01, Alexandre Mergnat ha scritto:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add IOMMU binding documentation for the MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
> .../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
> include/dt-bindings/memory/mt8365-larb-port.h | 90 ++++++++++++++++++++++
> 2 files changed, 92 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index fee0241b5098..4b8cf3ce6963 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -81,6 +81,7 @@ properties:
> - mediatek,mt8195-iommu-vdo # generation two
> - mediatek,mt8195-iommu-vpp # generation two
> - mediatek,mt8195-iommu-infra # generation two
> + - mediatek,mt8365-m4u # generation two
>
> - description: mt7623 generation one
> items:
> @@ -130,6 +131,7 @@ properties:
> dt-binding/memory/mt8186-memory-port.h for mt8186,
> dt-binding/memory/mt8192-larb-port.h for mt8192.
> dt-binding/memory/mt8195-memory-port.h for mt8195.
> + dt-binding/memory/mt8365-larb-port.h for mt8365.
>
> power-domains:
> maxItems: 1
> diff --git a/include/dt-bindings/memory/mt8365-larb-port.h b/include/dt-bindings/memory/mt8365-larb-port.h
> new file mode 100644
> index 000000000000..56d5a5dd519e
> --- /dev/null
> +++ b/include/dt-bindings/memory/mt8365-larb-port.h
Let's start using the correct filenames for memory bindings as well, shall we?
Please rename this file to mediatek,mt8365-larb-port.h
Thanks,
Angelo
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
2022-10-04 10:01 ` [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
2022-10-04 12:01 ` AngeloGioacchino Del Regno
@ 2022-10-06 9:29 ` Markus Schneider-Pargmann
1 sibling, 0 replies; 9+ messages in thread
From: Markus Schneider-Pargmann @ 2022-10-06 9:29 UTC (permalink / raw)
To: Alexandre Mergnat
Cc: Rob Herring, Yong Wu, Matthias Brugger, Will Deacon,
Joerg Roedel, Robin Murphy, Krzysztof Kozlowski, linux-kernel,
linux-mediatek, linux-arm-kernel, Fabien Parent,
Amjad Ouled-Ameur, devicetree, iommu
Hi Alexandre,
On Tue, Oct 04, 2022 at 12:01:39PM +0200, Alexandre Mergnat wrote:
> From: Fabien Parent <fparent@baylibre.com>
>
> Add IOMMU binding documentation for the MT8365 SoC.
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
> .../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
> include/dt-bindings/memory/mt8365-larb-port.h | 90 ++++++++++++++++++++++
> 2 files changed, 92 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index fee0241b5098..4b8cf3ce6963 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -81,6 +81,7 @@ properties:
> - mediatek,mt8195-iommu-vdo # generation two
> - mediatek,mt8195-iommu-vpp # generation two
> - mediatek,mt8195-iommu-infra # generation two
> + - mediatek,mt8365-m4u # generation two
This comment should probably be aligned with the ones above.
Best,
Markus
>
> - description: mt7623 generation one
> items:
> @@ -130,6 +131,7 @@ properties:
> dt-binding/memory/mt8186-memory-port.h for mt8186,
> dt-binding/memory/mt8192-larb-port.h for mt8192.
> dt-binding/memory/mt8195-memory-port.h for mt8195.
> + dt-binding/memory/mt8365-larb-port.h for mt8365.
>
> power-domains:
> maxItems: 1
> diff --git a/include/dt-bindings/memory/mt8365-larb-port.h b/include/dt-bindings/memory/mt8365-larb-port.h
> new file mode 100644
> index 000000000000..56d5a5dd519e
> --- /dev/null
> +++ b/include/dt-bindings/memory/mt8365-larb-port.h
> @@ -0,0 +1,90 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Yong Wu <yong.wu@mediatek.com>
> + */
> +#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
> +#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
> +
> +#include <dt-bindings/memory/mtk-memory-port.h>
> +
> +#define M4U_LARB0_ID 0
> +#define M4U_LARB1_ID 1
> +#define M4U_LARB2_ID 2
> +#define M4U_LARB3_ID 3
> +
> +/* larb0 */
> +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
> +#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1)
> +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
> +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
> +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
> +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
> +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6)
> +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
> +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8)
> +#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9)
> +#define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10)
> +#define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11)
> +
> +/* larb1 */
> +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0)
> +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 1)
> +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 2)
> +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB1_ID, 3)
> +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 4)
> +#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB1_ID, 5)
> +#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 6)
> +#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB1_ID, 7)
> +#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB1_ID, 8)
> +#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB1_ID, 9)
> +#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 10)
> +#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB1_ID, 11)
> +#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 12)
> +#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB1_ID, 13)
> +#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 14)
> +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 15)
> +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 16)
> +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 17)
> +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 18)
> +
> +/* larb2 */
> +#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0)
> +#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1)
> +#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2)
> +#define M4U_PORT_CAM_LCS MTK_M4U_ID(M4U_LARB2_ID, 3)
> +#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4)
> +#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(M4U_LARB2_ID, 5)
> +#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(M4U_LARB2_ID, 6)
> +#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 7)
> +#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 8)
> +#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB2_ID, 9)
> +#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB2_ID, 10)
> +#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 11)
> +#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 12)
> +#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 13)
> +#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 14)
> +#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 15)
> +#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 16)
> +#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(M4U_LARB2_ID, 17)
> +#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(M4U_LARB2_ID, 18)
> +#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(M4U_LARB2_ID, 19)
> +#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(M4U_LARB2_ID, 20)
> +#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(M4U_LARB2_ID, 21)
> +#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(M4U_LARB2_ID, 22)
> +#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(M4U_LARB2_ID, 23)
> +
> +/* larb3 */
> +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB3_ID, 0)
> +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB3_ID, 1)
> +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB3_ID, 2)
> +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB3_ID, 3)
> +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB3_ID, 4)
> +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB3_ID, 5)
> +#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB3_ID, 6)
> +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB3_ID, 7)
> +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB3_ID, 8)
> +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB3_ID, 9)
> +#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10)
> +
> +#endif
>
> --
> b4 0.10.1
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/3] iommu/mediatek: add support for 6-bit encoded port IDs
2022-10-04 11:59 ` AngeloGioacchino Del Regno
@ 2022-10-06 10:46 ` Robin Murphy
0 siblings, 0 replies; 9+ messages in thread
From: Robin Murphy @ 2022-10-06 10:46 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Alexandre Mergnat, Rob Herring,
Yong Wu, Matthias Brugger, Will Deacon, Joerg Roedel,
Krzysztof Kozlowski
Cc: linux-kernel, linux-mediatek, linux-arm-kernel, Fabien Parent,
Markus Schneider-Pargmann, Amjad Ouled-Ameur, devicetree, iommu
On 2022-10-04 12:59, AngeloGioacchino Del Regno wrote:
> Il 04/10/22 12:01, Alexandre Mergnat ha scritto:
>> From: Fabien Parent <fparent@baylibre.com>
>>
>> Until now the port ID was always encoded as a 5-bit data. On MT8365,
>> the port ID is encoded as a 6-bit data. This requires to rework the
>> macros F_MMU_INT_ID_LARB_ID, and F_MMU_INT_ID_PORT_ID in order
>> to support 5-bit and 6-bit encoded port IDs.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
>> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
>> ---
>> drivers/iommu/mtk_iommu.c | 24 ++++++++++++++++++++----
>> 1 file changed, 20 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
>> index 5a4e00e4bbbc..a57ce509c8b5 100644
>> --- a/drivers/iommu/mtk_iommu.c
>> +++ b/drivers/iommu/mtk_iommu.c
>> @@ -108,8 +108,10 @@
>> #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
>> #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
>> #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
>> -#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
>> -#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
>> +#define F_MMU_INT_ID_LARB_ID(a, int_id_port_width) \
>> + ((a) >> (((int_id_port_width) + 2) & 0x7))
>> +#define F_MMU_INT_ID_PORT_ID(a, int_id_port_width) \
>> + (((a) >> 2) & GENMASK((int_id_port_width) - 1, 0))
>
> I can't think about any cleaner way than this one, but that's decreasing
> human
> readability by "quite a bit".
In terms of readability, the best thing to do would be define separate
macros for each register format and make the choice at the (single)
callsite rather than hiding it in the macro. In fact we're already doing
exactly that with the HAS_SUB_COMM_2BITS and HAS_SUB_COMM_3BITS flags
right at the same point, so please follow that same pattern for consistency.
Thanks,
Robin.
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-10-06 10:47 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-04 10:01 [PATCH v2 0/3] iommu/mediatek: Add mt8365 iommu support Alexandre Mergnat
2022-10-04 10:01 ` [PATCH v2 1/3] dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC Alexandre Mergnat
2022-10-04 12:01 ` AngeloGioacchino Del Regno
2022-10-06 9:29 ` Markus Schneider-Pargmann
2022-10-04 10:01 ` [PATCH v2 2/3] iommu/mediatek: add support for 6-bit encoded port IDs Alexandre Mergnat
2022-10-04 11:59 ` AngeloGioacchino Del Regno
2022-10-06 10:46 ` Robin Murphy
2022-10-04 10:01 ` [PATCH v2 3/3] iommu/mediatek: add support for MT8365 SoC Alexandre Mergnat
2022-10-04 12:00 ` AngeloGioacchino Del Regno
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