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Thu, 06 Oct 2022 05:26:48 -0700 (PDT) Date: Thu, 6 Oct 2022 15:26:46 +0300 From: Serge Semin To: Krzysztof Kozlowski Cc: Rob Herring , Serge Semin , Dinh Nguyen , Michail Ivanov , James Morse , Michal Simek , Tony Luck , Punnaiah Choudary Kalluri , linux-edac@vger.kernel.org, Borislav Petkov , Robert Richter , Alexey Malahov , linux-arm-kernel@lists.infradead.org, Pavel Parkhomenko , linux-kernel@vger.kernel.org, Mauro Carvalho Chehab , Manish Narani , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org Subject: Re: [PATCH v3 02/13] dt-bindings: memory: Add Baikal-T1 DDRC DT-schema Message-ID: <20221006122646.u3vi4xwgo3yswyxj@mobilestation> References: <20220929234121.13955-1-Sergey.Semin@baikalelectronics.ru> <20220929234121.13955-3-Sergey.Semin@baikalelectronics.ru> <166479586876.1658787.6925988592765037866.robh@kernel.org> <3ee1bff2-ab11-2dcd-aede-628d2735d6de@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3ee1bff2-ab11-2dcd-aede-628d2735d6de@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221006_052652_166428_40EA06AA X-CRM114-Status: GOOD ( 22.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 05, 2022 at 04:59:52PM +0200, Krzysztof Kozlowski wrote: > On 03/10/2022 15:24, Rob Herring wrote: > > On Fri, 30 Sep 2022 02:41:10 +0300, Serge Semin wrote: > >> Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a > >> with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There > >> are individual IRQs for each ECC and DFI events. The dedicated scrubber > >> clock source is absent since it's fully synchronous to the core clock. > >> In addition to that the DFI-DDR PHY CSRs can be accessed via a separate > >> registers space. > >> > >> Signed-off-by: Serge Semin > >> Reviewed-by: Rob Herring > >> > >> --- > >> > >> Changelog v2: > >> - Keep the alphabetically ordered compatible strings list. (@Krzysztof) > >> - Fix grammar nitpicks in the patch log. (@Krzysztof) > >> - Drop the PHY CSR region. (@Rob) > >> - Move the device bindings to the separate DT-schema. > >> --- > >> .../memory-controllers/baikal,bt1-ddrc.yaml | 91 +++++++++++++++++++ > >> 1 file changed, 91 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml > >> > > > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > > > yamllint warnings/errors: > > > > dtschema/dtc warnings/errors: > > ./Documentation/devicetree/bindings/memory-controllers/baikal,bt1-ddrc.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-common.yaml > > This is result of patch #1 failing to apply: > > https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20220929234121.13955-2-Sergey.Semin@baikalelectronics.ru/ I couldn't parse the patch-applied log < error: sha1 information is lacking or useless (Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml). < error: could not build fake ancestor < hint: Use 'git am --show-current-patch=diff' to see the failed patch What does it mean? -Sergey > > The bindings look ok, but anyway it is a merge window now. > > > Best regards, > Krzysztof > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel