From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 994B3C77B7F for ; Tue, 16 May 2023 13:31:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=4+J6p8fI1Ii+De1wCAv1XoMYu1d4svU/DKFLq8B/39A=; b=viym+SCQx9XlTW qyipavQobIbuIfg2ppxzXUSNQ2Zfdqxg7hnCEkBLaVvEsdEmPTg9jT8jVx7/5K7rBCFmQ9Y3FwGoM oySDOg+syxr9LLqDn7YmaZYGOJlyWzSCf4czlouKVGg0YCsGvVNN7Mwry7rw27PwM73CQyDmfbKh8 cryTHk+SLz5LGwzHx0GF6ehuy9YmAqAPCK+02ZguUxvmY1bEgt3d7MCwDbYnXuWsl66UuwLiWcGGp qzCyLX6jISBiTPBAOi1lkmGD0k0riTKU50SbGZ0Vh+7FBl9SVG8alc3GEbXs5hZcoBqXGWOHIrKsd nVJlZ0XojCZu1dDuYkVg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pyum0-005vfs-36; Tue, 16 May 2023 13:31:28 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pyuly-005vdx-0K for linux-arm-kernel@lists.infradead.org; Tue, 16 May 2023 13:31:27 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 34GDV1Px029662; Tue, 16 May 2023 08:31:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1684243861; bh=KiJOZ7KFupaQDkC6vwpyzXkB38VvgH/7nK2KElIdK5Q=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=qmxDx+vKWF7bJ3554Yy0ba71FC9/2fR6vrCrPeeSZl3jvce7FcmFk6BJoWt7v1/JW tfa1G+VAhjq/FEqTZDLrxRaX876MWicoUDOCAl35rq68ejM1UkvQ/MSoiiiNaF0HN9 Y7QIBDlSmepMghOqmqhD0zIF8Nrnw40ObNtxyrgc= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 34GDV1jx020884 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 16 May 2023 08:31:01 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 16 May 2023 08:31:01 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 16 May 2023 08:31:01 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 34GDV1wZ031938; Tue, 16 May 2023 08:31:01 -0500 Date: Tue, 16 May 2023 08:31:01 -0500 From: Nishanth Menon To: Siddharth Vadapalli , Peter Rosin , CC: , , , , , , , , , , , , , , , Subject: Re: [PATCH net-next 4/5] arm64: dts: ti: k3-am62-main: Add timesync router node Message-ID: <20230516133101.ezt5jacp6i47nspa@oblivion> References: <20230111114429.1297557-1-s-vadapalli@ti.com> <20230111114429.1297557-5-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20230111114429.1297557-5-s-vadapalli@ti.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230516_063126_222801_CFBB95AD X-CRM114-Status: GOOD ( 17.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 17:14-20230111, Siddharth Vadapalli wrote: > TI's AM62x SoC has a Time Sync Event Router, which enables routing a single > input signal to multiple recipients. This facilitates syncing all the > peripherals or processor cores to the input signal which acts as a master > clock. > > Signed-off-by: Siddharth Vadapalli > --- > arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > index 072903649d6e..4ce59170b6a7 100644 > --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi > @@ -649,6 +649,15 @@ cpts@3d000 { > }; > }; > > + timesync_router: pinctrl@a40000 { > + compatible = "pinctrl-single"; While I understand that the timesync router is essentially a mux, pinctrl-single is a specific mux model that is used to model external facing pins to internal signals - pin mux sections of control module which is already in place is an example of the same. Using the pinctrl-single scheme for timesync router is, IMHO, wrong and limiting to potential functions that timesync router could need enabling. Is there a reason for using pinctrl-single rather than writing a mux-controller / consumer model driver instead or rather simpler a reg-mux node? > + reg = <0x0 0xa40000 0x0 0x800>; > + #pinctrl-cells = <1>; > + pinctrl-single,register-width = <32>; > + pinctrl-single,function-mask = <0x000107ff>; > + status = "disabled"; > + }; > + -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel