From: Bjorn Helgaas <helgaas@kernel.org>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>,
bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
thierry.reding@gmail.com, jonathanh@nvidia.com,
Kishon Vijay Abraham I <kishon@kernel.org>,
catalin.marinas@arm.com, Will Deacon <will@kernel.org>,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
digetx@gmail.com, mperttunen@nvidia.com,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH V16 13/13] PCI: tegra: Add Tegra194 PCIe support
Date: Wed, 14 Feb 2024 13:12:49 -0600 [thread overview]
Message-ID: <20240214191249.GA1263222@bhelgaas> (raw)
In-Reply-To: <20190813113627.27251-14-vidyas@nvidia.com>
Hi Vidya, question about ancient history:
On Tue, Aug 13, 2019 at 05:06:27PM +0530, Vidya Sagar wrote:
> Add support for Synopsys DesignWare core IP based PCIe host controller
> present in Tegra194 SoC.
> ...
> +static int tegra_pcie_dw_host_init(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
> + u32 val, tmp, offset, speed;
> +
> + tegra_pcie_prepare_host(pp);
> +
> + if (dw_pcie_wait_for_link(pci)) {
> + /*
> + * There are some endpoints which can't get the link up if
> + * root port has Data Link Feature (DLF) enabled.
> + * Refer Spec rev 4.0 ver 1.0 sec 3.4.2 & 7.7.4 for more info
> + * on Scaled Flow Control and DLF.
> + * So, need to confirm that is indeed the case here and attempt
> + * link up once again with DLF disabled.
This comment suggests that there's an issue with *Endpoints*, not an
issue with the Root Port. If so, it seems like this problem could
occur with all Root Ports, not just Tegra194. Do you remember any
details about this?
I don't remember hearing about any similar issues, and this driver is
the only place PCI_EXT_CAP_ID_DLF is referenced, so maybe it is
actually something related to Tegra194?
> + val = appl_readl(pcie, APPL_DEBUG);
> + val &= APPL_DEBUG_LTSSM_STATE_MASK;
> + val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
> + tmp = appl_readl(pcie, APPL_LINK_STATUS);
> + tmp &= APPL_LINK_STATUS_RDLH_LINK_UP;
> + if (!(val == 0x11 && !tmp)) {
> + /* Link is down for all good reasons */
> + return 0;
> + }
> +
> + dev_info(pci->dev, "Link is down in DLL");
> + dev_info(pci->dev, "Trying again with DLFE disabled\n");
> + /* Disable LTSSM */
> + val = appl_readl(pcie, APPL_CTRL);
> + val &= ~APPL_CTRL_LTSSM_EN;
> + appl_writel(pcie, val, APPL_CTRL);
> +
> + reset_control_assert(pcie->core_rst);
> + reset_control_deassert(pcie->core_rst);
> +
> + offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF);
> + val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
> + val &= ~PCI_DLF_EXCHANGE_ENABLE;
> + dw_pcie_writel_dbi(pci, offset, val);
> +
> + tegra_pcie_prepare_host(pp);
> +
> + if (dw_pcie_wait_for_link(pci))
> + return 0;
> + }
> +
> + speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
> + PCI_EXP_LNKSTA_CLS;
> + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
> +
> + tegra_pcie_enable_interrupts(pp);
> +
> + return 0;
> +}
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next prev parent reply other threads:[~2024-02-14 19:13 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-13 11:36 [PATCH V16 00/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 01/13] PCI: Add #defines for some of PCIe spec r4.0 features Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 02/13] PCI: Disable MSI for Tegra root ports Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 03/13] PCI: dwc: Perform dbi regs write lock towards the end Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 04/13] PCI: dwc: Move config space capability search API Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 05/13] PCI: dwc: Add ext " Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 06/13] PCI: dwc: Export dw_pcie_wait_for_link() API Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 07/13] dt-bindings: PCI: designware: Add binding for CDM register check Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 08/13] PCI: dwc: Add support to enable " Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 09/13] dt-bindings: Add PCIe supports-clkreq property Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 10/13] dt-bindings: PCI: tegra: Add device tree support for Tegra194 Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 11/13] dt-bindings: PHY: P2U: Add Tegra194 P2U block Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 12/13] phy: tegra: Add PCIe PIPE2UPHY support Vidya Sagar
2019-08-13 11:36 ` [PATCH V16 13/13] PCI: tegra: Add Tegra194 PCIe support Vidya Sagar
2024-02-14 19:12 ` Bjorn Helgaas [this message]
2024-02-15 11:25 ` Vidya Sagar
2024-02-15 16:01 ` Bjorn Helgaas
2024-02-15 19:09 ` Vidya Sagar
2019-08-13 16:33 ` [PATCH V16 00/13] " Lorenzo Pieralisi
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