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([2a0b:e7c0:0:107::70f]) by smtp.gmail.com with ESMTPSA id a11sm1663829wrx.38.2021.05.19.22.25.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 19 May 2021 22:25:14 -0700 (PDT) Subject: Re: [PATCH v3 2/2] serial: 8250: Use BIT(x) for UART_{CAP,BUG}_* To: Andrew Jeffery , linux-serial@vger.kernel.org Cc: gregkh@linuxfoundation.org, joel@jms.id.au, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, jenmin_yuan@aspeedtech.com, ryan_chen@aspeedtech.com, miltonm@us.ibm.com References: <20210520021334.497341-1-andrew@aj.id.au> <20210520021334.497341-3-andrew@aj.id.au> From: Jiri Slaby Message-ID: <20eec190-d80e-b32a-8949-e5e2918a110b@kernel.org> Date: Thu, 20 May 2021 07:25:13 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <20210520021334.497341-3-andrew@aj.id.au> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210519_222516_830130_51098117 X-CRM114-Status: GOOD ( 17.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 20. 05. 21, 4:13, Andrew Jeffery wrote: > BIT(x) improves readability and safety with respect to shifts. > > Signed-off-by: Andrew Jeffery Reviewed-by: Jiri Slaby > --- > drivers/tty/serial/8250/8250.h | 33 +++++++++++++++++---------------- > 1 file changed, 17 insertions(+), 16 deletions(-) > > diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h > index 34aa2714f3c9..6473361525d1 100644 > --- a/drivers/tty/serial/8250/8250.h > +++ b/drivers/tty/serial/8250/8250.h > @@ -7,6 +7,7 @@ > * Copyright (C) 2001 Russell King. > */ > > +#include > #include > #include > #include > @@ -70,25 +71,25 @@ struct serial8250_config { > unsigned int flags; > }; > > -#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */ > -#define UART_CAP_EFR (1 << 9) /* UART has EFR */ > -#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */ > -#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */ > -#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */ > -#define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */ > -#define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */ > -#define UART_CAP_RPM (1 << 15) /* Runtime PM is active while idle */ > -#define UART_CAP_IRDA (1 << 16) /* UART supports IrDA line discipline */ > -#define UART_CAP_MINI (1 << 17) /* Mini UART on BCM283X family lacks: > +#define UART_CAP_FIFO BIT(8) /* UART has FIFO */ > +#define UART_CAP_EFR BIT(9) /* UART has EFR */ > +#define UART_CAP_SLEEP BIT(10) /* UART has IER sleep */ > +#define UART_CAP_AFE BIT(11) /* MCR-based hw flow control */ > +#define UART_CAP_UUE BIT(12) /* UART needs IER bit 6 set (Xscale) */ > +#define UART_CAP_RTOIE BIT(13) /* UART needs IER bit 4 set (Xscale, Tegra) */ > +#define UART_CAP_HFIFO BIT(14) /* UART has a "hidden" FIFO */ > +#define UART_CAP_RPM BIT(15) /* Runtime PM is active while idle */ > +#define UART_CAP_IRDA BIT(16) /* UART supports IrDA line discipline */ > +#define UART_CAP_MINI BIT(17) /* Mini UART on BCM283X family lacks: > * STOP PARITY EPAR SPAR WLEN5 WLEN6 > */ > > -#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */ > -#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */ > -#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */ > -#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */ > -#define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */ > -#define UART_BUG_TXRACE (1 << 5) /* UART Tx fails to set remote DR */ > +#define UART_BUG_QUOT BIT(0) /* UART has buggy quot LSB */ > +#define UART_BUG_TXEN BIT(1) /* UART has buggy TX IIR status */ > +#define UART_BUG_NOMSR BIT(2) /* UART has buggy MSR status bits (Au1x00) */ > +#define UART_BUG_THRE BIT(3) /* UART has buggy THRE reassertion */ > +#define UART_BUG_PARITY BIT(4) /* UART mishandles parity if FIFO enabled */ > +#define UART_BUG_TXRACE BIT(5) /* UART Tx fails to set remote DR */ > > > #ifdef CONFIG_SERIAL_8250_SHARE_IRQ > -- js suse labs _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel