From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.6 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30F74C433E9 for ; Mon, 8 Feb 2021 15:03:49 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C14A464E9A for ; Mon, 8 Feb 2021 15:03:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C14A464E9A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From: Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=bknA8/S5/nLNQu9Fqdso3B0poIf+TNu72vjFoYfnEZ0=; b=aqzfFJrujVwwErh55A2iHiq5w pWOF4+tHfTdVAD9PKu5wk/0us9f1JM6J7MxG8f5zF/u0pBLzOlIuf7KuFndqB0YGs4yVu/qMQsSms n64IPjo5HzUMI6fJGTy69ulaK5AipG3j8chlTvW6pY0ztKv/3C8vya5ZmDtv6W2sI66fbE5S+WK5T A60rnVt1SVNMr2+77fR/6WY5TqLkvsH/3bkVqLFBzwi0FpEf77+af0tnO+U1crKoMbaN3EJLpaV5g v5h92TAkHBU+W3EgCrVGeSJu/efF78unpBbuj5DTMALKmAku7CpQZ93pSk2Zzko32Nc5DJbdOYqY7 gvADQauuw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l983Y-00038n-Bb; Mon, 08 Feb 2021 15:02:28 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l983V-000383-QG for linux-arm-kernel@lists.infradead.org; Mon, 08 Feb 2021 15:02:27 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 166F264E29; Mon, 8 Feb 2021 15:02:25 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1l983S-00CoV5-QY; Mon, 08 Feb 2021 15:02:23 +0000 MIME-Version: 1.0 Date: Mon, 08 Feb 2021 15:02:22 +0000 From: Marc Zyngier To: Will Deacon Subject: Re: [PATCH v7 00/23] arm64: Early CPU feature override, and applications to VHE, BTI and PAuth In-Reply-To: <20210208143248.GA25934@willie-the-truck> References: <20210208095732.3267263-1-maz@kernel.org> <20210208143248.GA25934@willie-the-truck> User-Agent: Roundcube Webmail/1.4.10 Message-ID: <240a0245f75d8368a4d90a5e6740dc7d@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: will@kernel.org, psodagud@codeaurora.org, sramana@codeaurora.org, catalin.marinas@arm.com, marcan@marcan.st, linux-kernel@vger.kernel.org, ardb@kernel.org, pajay@qti.qualcomm.com, kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210208_100226_399876_39FF676D X-CRM114-Status: GOOD ( 24.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Srinivas Ramana , Catalin Marinas , Hector Martin , linux-kernel@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Ajay Patil , Prasad Sodagudi , kernel-team@android.com, Ard Biesheuvel , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On 2021-02-08 14:32, Will Deacon wrote: > Hi Marc, > > On Mon, Feb 08, 2021 at 09:57:09AM +0000, Marc Zyngier wrote: >> It recently came to light that there is a need to be able to override >> some CPU features very early on, before the kernel is fully up and >> running. The reasons for this range from specific feature support >> (such as using Protected KVM on VHE HW, which is the main motivation >> for this work) to errata workaround (a feature is broken on a CPU and >> needs to be turned off, or rather not enabled). >> >> This series tries to offer a limited framework for this kind of >> problems, by allowing a set of options to be passed on the >> command-line and altering the feature set that the cpufeature >> subsystem exposes to the rest of the kernel. Note that this doesn't >> change anything for code that directly uses the CPU ID registers. > > I applied this locally, but I'm seeing consistent boot failure under > QEMU when > KASAN is enabled. I tried sprinkling some __no_sanitize_address > annotations > around (see below) but it didn't help. The culprit appears to be > early_fdt_map(), but looking a bit more closely, I'm really nervous > about the > way we call into C functions from __primary_switched. Remember -- this > code > runs _twice_ when KASLR is active: before and after the randomization. > This > also means that any memory writes the first time around can be lost due > to > the D-cache invalidation when (re-)creating the kernel page-tables. Well, we already call into C functions with KASLR, and nothing explodes with that, so I must be doing something else wrong. I do have cache maintenance for the writes to the shadow registers, so that part should be fine. But I think I'm missing some cache maintenance around the FDT base itself, and I wonder what happens when we go around the loop. I'll chase this down now. Thanks for the heads up. M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel