From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F687ECAAA1 for ; Fri, 9 Sep 2022 06:01:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Cc:To:From:Subject:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=VDnyHTJ1/KiwJcBxn4rBXsGSl1krjJ7W+tN/nerxIrE=; b=YJldsSBRQlpiGc 3kfJBAv03EvzKGnyqjGzAC0I3m80hw7fpT8aTh+KvjtMFVloy0BLjgotd3jY/rz+YXHehSXSafQX3 ZAPuidiQAz+IagP5M8CYkXme4LgO0GKCX80yeCx1KmW4x0XeNJaSfbtxMkamGrVET5ie4rgpAzUJa JQdtD1PYKoztG+4WzbIwOUkFCbohkzVC7CPAmtpFKeyY7YIkcJGBxWjSbo409f2xyOY9PWIQW+Byc orasAorta4st/ey2ycMhXTXT3LtB5CvrJ2643hlpDkrFZyXF9gfe+1cExKhZH/wDN+/p9Y7kySXOl DaP0X7wgS5J6PaFzoMDA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWX3c-00D0GX-Gr; Fri, 09 Sep 2022 06:00:04 +0000 Received: from mx1.tq-group.com ([93.104.207.81]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oWX3Y-00D0B3-S5 for linux-arm-kernel@lists.infradead.org; Fri, 09 Sep 2022 06:00:03 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1662703201; x=1694239201; h=subject:from:to:cc:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TUTNp7tl9jBH5gO6p63V0NMyQAOZJ1ygWfraWfAJrNc=; b=KVG+UgzG7nUYMe4+dHX/ZVDwYiP+TEib1r73g5BFdMH9i+20W4mfYZIq dLoRg6ziCcddcPeaMzeUFuYOBwd0FZkS8OsraKYRyGFHhNUQOEVT5jJwO Q+lXcuU/rg/OmXPTJFh+n1oj1Meny7+okcKNbnkjt0Veiq6hYk4pWNhsa va27ZPpmbbyS+T6PX8Afp7koQlkc3qJpDV1LSJhCOgbS5t1nSItmnk4Id sCL789fiWDZEpK/u2bAVWneojhA4apGsH/p8I9lp8BiAm9eVRtwExEco3 64m3Qw9OqnMchjV254+ZxFFAEYSAwClUxcjHGwf4KhRsJit/de8JUf8sc Q==; X-IronPort-AV: E=Sophos;i="5.93,302,1654552800"; d="scan'208";a="26081637" Received: from unknown (HELO tq-pgp-pr1.tq-net.de) ([192.168.6.15]) by mx1-pgp.tq-group.com with ESMTP; 09 Sep 2022 07:59:54 +0200 Received: from mx1.tq-group.com ([192.168.6.7]) by tq-pgp-pr1.tq-net.de (PGP Universal service); Fri, 09 Sep 2022 07:59:54 +0200 X-PGP-Universal: processed; by tq-pgp-pr1.tq-net.de on Fri, 09 Sep 2022 07:59:54 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1662703194; x=1694239194; h=from:to:cc:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding:subject; bh=TUTNp7tl9jBH5gO6p63V0NMyQAOZJ1ygWfraWfAJrNc=; b=AxeWm9HI5bnejNpj7Z7edWKWGzR0EVA6/0v1TRV/yqJqfOc8RqK/xJKK j4I32uEkLFqFDO0e/MSnqZrct4idEozUIvP/xEW4sW6AxmAS5RY6XTd9b RYLJ4RsPGyzYlj3w3dUG4m7Fh9lKTLezdhSWg31sehyJndFDiNFQrMFHr 92BTBGsRl1cV1hxfKI2Gj6slmdjuqQOM0jpbgMCR2/Q5+F3HZBw/plH9G kRAj2L7KvgADOI9LMmpxg6Lyq+trbLt9vI1GdTVccU77S3uYbt+ZNN4o3 CNqqD2DzfGV2Cfz2DflhwOxgFz+ZUi0Qw2O6XGzk3fzgKt+f9fsnPcCs8 A==; X-IronPort-AV: E=Sophos;i="5.93,302,1654552800"; d="scan'208";a="26081636" Subject: Re: [PATCH] arm64: dts: imx8mp-venice-gw74xx: add PCIe support Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 09 Sep 2022 07:59:54 +0200 Received: from steina-w.localnet (unknown [10.123.49.11]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id 5695B280056; Fri, 9 Sep 2022 07:59:54 +0200 (CEST) From: Alexander Stein To: Tim Harvey Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, NXP Linux Team , Fabio Estevam , Pengutronix Kernel Team , Sascha Hauer , Shawn Guo , Krzysztof Kozlowski , Rob Herring , Tim Harvey Date: Fri, 09 Sep 2022 07:59:52 +0200 Message-ID: <2530681.Lt9SDvczpP@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20220908154903.4100386-1-tharvey@gateworks.com> References: <20220908154903.4100386-1-tharvey@gateworks.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220908_230001_327866_F4E4444C X-CRM114-Status: GOOD ( 19.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Tim, Am Donnerstag, 8. September 2022, 17:49:03 CEST schrieb Tim Harvey: > Add PCIe support on the Gateworks GW74xx board. While at it, > fix the related gpio line names from the previous incorrect values. > > Signed-off-by: Tim Harvey > --- > .../dts/freescale/imx8mp-venice-gw74xx.dts | 40 +++++++++++++++++-- > 1 file changed, 37 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index > e0fe356b662d..7644db61d631 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > > #include "imx8mp.dtsi" > > @@ -100,6 +101,12 @@ led-1 { > }; > }; > > + pcie0_refclk: pcie0-refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <100000000>; > + }; > + > pps { > compatible = "pps-gpio"; > pinctrl-names = "default"; > @@ -215,8 +222,8 @@ &gpio1 { > &gpio2 { > gpio-line-names = > "", "", "", "", "", "", "", "", > - "", "", "", "", "", "", "", "", > - "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", > + "", "", "", "", "", "", "pcie3_wdis#", "", > + "", "", "pcie2_wdis#", "", "", "", "", "", > "", "", "", "", "", "", "", ""; > }; > > @@ -562,6 +569,28 @@ &i2c4 { > status = "okay"; > }; > > +&pcie_phy { > + fsl,refclk-pad-mode = ; > + fsl,clkreq-unsupported; > + clocks = <&pcie0_refclk>; > + clock-names = "ref"; > + status = "okay"; > +}; > + > +&pcie { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie0>; > + reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>; > + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, > + <&clk IMX8MP_CLK_PCIE_ROOT>, > + <&clk IMX8MP_CLK_HSIO_AXI>; > + clock-names = "pcie", "pcie_aux", "pcie_bus"; With the still pending dt-binding patch at [1] the clock order shall be "pcie", "pcie_bus", "pcie_phy". Best regards, Alexander [1] https://lore.kernel.org/lkml/20220822184701.25246-2-Sergey.Semin@baikalelectronics.ru/ > + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; > + assigned-clock-rates = <10000000>; > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; > + status = "okay"; > +}; > + > /* GPS / off-board header */ > &uart1 { > pinctrl-names = "default"; > @@ -694,7 +723,6 @@ pinctrl_hog: hoggrp { > MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ > MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ > MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 / * M2SKT_OFF# */ > - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */ > MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ > MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 / * PCIE3_WDIS# */ > MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ > @@ -807,6 +835,12 @@ MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10 > > >; > > }; > > + pinctrl_pcie0: pciegrp { > + fsl,pins = < > + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 > + >; > + }; > + > pinctrl_pmic: pmicgrp { > fsl,pins = < > MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel