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Wed, 5 Feb 2020 11:26:16 +0100 (CET) Subject: Re: STM32MP1 level triggered interrupts From: Marek Vasut To: Marc Zyngier , Alexandre Torgue References: <20bb72d0-8258-abc0-e729-4d3d5a75c41c@denx.de> <65a1c5b2-c1b9-322f-338c-e6ff6379d8d1@denx.de> <129d04a0-c846-506d-5726-4a1024d977a6@st.com> <80db762c-3b3d-f007-2f9b-dadbffd95782@denx.de> <360b1adc-32f1-7993-c463-e52c7a5a8a67@st.com> <20200123101225.nscpc5t4nmlarbw2@pengutronix.de> <03fd1cb7b5985b3221f66c6b0058adc8@kernel.org> <20200123105214.ru4j76xbisjtbtgw@pengutronix.de> <7e0ce712f7e34b38c8f541644026c52e@kernel.org> <5e1c419c-b141-52f6-88f1-ee3ab8219a4e@denx.de> Message-ID: <2a86d71f-3e64-8f66-3e58-df540487dcb4@denx.de> Date: Wed, 5 Feb 2020 11:26:16 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.2 MIME-Version: 1.0 In-Reply-To: <5e1c419c-b141-52f6-88f1-ee3ab8219a4e@denx.de> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200205_022621_168821_56F91B79 X-CRM114-Status: GOOD ( 14.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linux ARM , linux-stm32@st-md-mailman.stormreply.com, Maxime Coquelin , Patrick Delaunay , =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 1/28/20 7:32 PM, Marek Vasut wrote: > On 1/24/20 10:24 AM, Marc Zyngier wrote: >> On 2020-01-24 09:17, Alexandre Torgue wrote: >>> On 1/23/20 11:21 PM, Marek Vasut wrote: >> >> [...] >> >>>> But I still wonder, what is the purpose of the EXTImux in that SoC? >>>> Shouldn't that permit routing GPIOs directly into GIC SPIs, which would >>>> then permit detecting at least level-high interrupts ? >>>> >>> >>> For this SoC, EXTI block detects external line edges and rises a GIC >>> SPI interrupt. This EXTi block is mainly used to handle HW events like >>> buttons, clocks ... So first issue seems more to be a design issue >>> (your design doesn't fit with MP1 datasheet). >>> >>> Now, let's find a solution. I'll have a look on your proposition: >>> "check the line in EOI callback and retrig". >>> >>> Marc, this kind a solution could be acceptable on your side ? >> >> It will depend on the nature of the hack you will have to put in there. >> If it is 100% reliable, why not? Anything short of that, probably not. > > I had another look into this, and what we would end up is some sort of > phandle from exti to all the gpioX nodes in DT, would that be OK ? > However, if we do that, then we will have the pinctrl controller (which > has the gpio banks as subnodes) require the exti through a phandle and > exti require the gpio banks through a phandle, so we end up with some > sort of cyclic dependency there. > > So we would need to somehow have exti lazily deal with it's gpioX > controller phandles only when someone requests level interrupt ? That > would probably do. Bump? Thoughts? _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel