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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id d6sm5686326wrx.60.2021.12.04.06.14.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 04 Dec 2021 06:14:03 -0800 (PST) Subject: Re: [RFC PATCH v3 09/29] KVM: arm64: Hide IMPLEMENTATION DEFINED PMU support for the guest To: Reiji Watanabe Cc: kvm@vger.kernel.org, Marc Zyngier , Peter Shier , Paolo Bonzini , Will Deacon , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org References: <20211117064359.2362060-1-reijiw@google.com> <20211117064359.2362060-10-reijiw@google.com> <5bd01c9c-6ac8-4034-6f49-be636a3b287c@redhat.com> From: Eric Auger Message-ID: <2ed3072b-f83d-1b17-0949-ca38267ba94e@redhat.com> Date: Sat, 4 Dec 2021 15:14:01 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eauger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211204_061410_815384_112556D9 X-CRM114-Status: GOOD ( 21.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Reiji, On 12/4/21 2:04 AM, Reiji Watanabe wrote: > Hi Eric, > > On Thu, Dec 2, 2021 at 2:57 AM Eric Auger wrote: >> >> Hi Reiji, >> >> On 11/30/21 6:32 AM, Reiji Watanabe wrote: >>> Hi Eric, >>> >>> On Thu, Nov 25, 2021 at 12:30 PM Eric Auger wrote: >>>> >>>> Hi Reiji, >>>> >>>> On 11/17/21 7:43 AM, Reiji Watanabe wrote: >>>>> When ID_AA64DFR0_EL1.PMUVER or ID_DFR0_EL1.PERFMON is 0xf, which >>>>> means IMPLEMENTATION DEFINED PMU supported, KVM unconditionally >>>>> expose the value for the guest as it is. Since KVM doesn't support >>>>> IMPLEMENTATION DEFINED PMU for the guest, in that case KVM should >>>>> exopse 0x0 (PMU is not implemented) instead. >>>> s/exopse/expose >>>>> >>>>> Change cpuid_feature_cap_perfmon_field() to update the field value >>>>> to 0x0 when it is 0xf. >>>> is it wrong to expose the guest with a Perfmon value of 0xF? Then the >>>> guest should not use it as a PMUv3? >>> >>>> is it wrong to expose the guest with a Perfmon value of 0xF? Then the >>>> guest should not use it as a PMUv3? >>> >>> For the value 0xf in ID_AA64DFR0_EL1.PMUVER and ID_DFR0_EL1.PERFMON, >>> Arm ARM says: >>> "IMPLEMENTATION DEFINED form of performance monitors supported, >>> PMUv3 not supported." >>> >>> Since the PMU that KVM supports for guests is PMUv3, 0xf shouldn't >>> be exposed to guests (And this patch series doesn't allow userspace >>> to set the fields to 0xf for guests). >> What I don't get is why this isn't detected before (in kvm_reset_vcpu). >> if the VCPU was initialized with KVM_ARM_VCPU_PMU_V3 can we honor this >> init request if the host pmu is implementation defined? > > KVM_ARM_VCPU_INIT with KVM_ARM_VCPU_PMU_V3 will fail in > kvm_reset_vcpu() if the host PMU is implementation defined. OK. This was not obvsious to me. if (kvm_vcpu_has_pmu(vcpu) && !kvm_arm_support_pmu_v3()) { ret = -EINVAL; goto out; } kvm_perf_init + if (perf_num_counters() > 0) + static_branch_enable(&kvm_arm_pmu_available); But I believe you ;-), sorry for the noise Eric > > The AA64DFR0 and DFR0 registers for a vCPU without KVM_ARM_VCPU_PMU_V3 > indicates IMPLEMENTATION DEFINED PMU support, which is not correct. > > Thanks, > Reiji > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel