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From: Marc Zyngier <maz@kernel.org>
To: Zenghui Yu <yuzenghui@huawei.com>
Cc: Jason Cooper <jason@lakedaemon.net>,
	Lokesh Vutla <lokeshvutla@ti.com>,
	John Garry <john.garry@huawei.com>,
	linux-kernel@vger.kernel.org,
	Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>,
	Rob Herring <robh+dt@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Thomas Gleixner <tglx@linutronix.de>,
	Julien Thierry <julien.thierry.kdev@gmail.com>
Subject: Re: [PATCH v2 04/12] irqchip/gic-v3: Add ESPI range support
Date: Tue, 20 Aug 2019 10:18:56 +0100	[thread overview]
Message-ID: <30fe07e9-0670-d755-2173-dc71549a797b@kernel.org> (raw)
In-Reply-To: <9cbd6fc8-3fe9-39fc-10ca-724a1ec06e8d@huawei.com>

On 19/08/2019 15:25, Zenghui Yu wrote:
> Hi Marc,
> 
> On 2019/8/6 18:01, Marc Zyngier wrote:
>> Add the required support for the ESPI range, which behave exactly like
>> the SPIs of old, only with new funky INTIDs.
>>
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>> ---
>>   drivers/irqchip/irq-gic-v3.c       | 85 ++++++++++++++++++++++++------
>>   include/linux/irqchip/arm-gic-v3.h | 17 +++++-
>>   2 files changed, 85 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
>> index db3bdedd7241..1ca4dde32034 100644
>> --- a/drivers/irqchip/irq-gic-v3.c
>> +++ b/drivers/irqchip/irq-gic-v3.c
>> @@ -51,13 +51,16 @@ struct gic_chip_data {
>>   	u32			nr_redist_regions;
>>   	u64			flags;
>>   	bool			has_rss;
>> -	unsigned int		irq_nr;
>>   	struct partition_desc	*ppi_descs[16];
>>   };
>>   
>>   static struct gic_chip_data gic_data __read_mostly;
>>   static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
>>   
>> +#define GIC_ID_NR	(1U << GICD_TYPER_ID_BITS(gic_data.rdists.gicd_typer))
>> +#define GIC_LINE_NR	GICD_TYPER_SPIS(gic_data.rdists.gicd_typer)
> 
> This indicates the maximum SPI INTID that the GIC implementation
> supports, should we restrict it to no more than 1020?

I guess we could write it as max(GICD_TYPER_SPIS(...), 1020), but that's
not a material change (the registers backing the special range do exist).

> ITLinesNumber can be '11111', and I saw the following info on my host:
>      "GICv3: 992 SPIs implemented"

Yeah, the above should fix the print.

Thanks,

	M.
-- 
Jazz is not dead, it just smells funny...

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  reply	other threads:[~2019-08-20  9:19 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-06 10:01 [PATCH v2 00/12] irqchip/gic-v3: Add support for GICv3.1 extended PPI/SPI ranges Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 01/12] irqchip/gic: Rework gic_configure_irq to take the full ICFGR base Marc Zyngier
2019-08-19 14:26   ` Zenghui Yu
2019-08-19 14:53     ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 02/12] irqchip/gic-v3: Add INTID range and convertion primitives Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 03/12] dt-bindings: interrupt-controller: arm, gic-v3: Describe ESPI range support Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 04/12] irqchip/gic-v3: Add " Marc Zyngier
2019-08-19 14:25   ` Zenghui Yu
2019-08-20  9:18     ` Marc Zyngier [this message]
2019-08-06 10:01 ` [PATCH v2 05/12] irqchip/gic: Prepare for more than 16 PPIs Marc Zyngier
2019-08-21 18:40   ` Zenghui Yu
2019-08-22 16:11   ` Julien
2019-08-22 16:32     ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 06/12] irqchip/gic-v3: Dynamically allocate PPI NMI refcounts Marc Zyngier
2019-08-22 15:05   ` Julien
2019-08-06 10:01 ` [PATCH v2 07/12] irqchip/gic-v3: Dynamically allocate PPI partition descriptors Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 08/12] dt-bindings: interrupt-controller: arm, gic-v3: Describe EPPI range support Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 09/12] irqchip/gic-v3: Add " Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 10/12] irqchip/gic-v3: Warn about inconsistent implementations of extended ranges Marc Zyngier
2019-08-06 10:15   ` Vladimir Murzin
2019-08-06 11:15     ` Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 11/12] irqchip/gic: Skip DT quirks when evaluating IIDR-based quirks Marc Zyngier
2019-08-06 10:01 ` [PATCH v2 12/12] irqchip/gic-v3: Add quirks for HIP06/07 invalid GICD_TYPER erratum 161010803 Marc Zyngier
2019-08-06 11:07   ` John Garry

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