From: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
To: Will Deacon <will.deacon@arm.com>
Cc: "eric.auger@redhat.com" <eric.auger@redhat.com>,
zhongmiao@hisilicon.com, okaya@kernel.org, rjw@rjwysocki.net,
linux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org,
sudeep.holla@arm.com, robin.murphy@arm.com,
linux-arm-kernel@lists.infradead.org, lenb@kernel.org
Subject: Re: [PATCH 2/4] iommu/arm-smmu-v3: Link domains and devices
Date: Fri, 5 Apr 2019 17:35:52 +0100 [thread overview]
Message-ID: <312d33a5-8eca-3fae-fd8b-8325e045761b@arm.com> (raw)
In-Reply-To: <20190404143924.GB27823@fuggles.cambridge.arm.com>
On 04/04/2019 15:39, Will Deacon wrote:
> Hi Jean-Philippe,
>
> First off, thanks for posting this: it's definitely something that I'm keen
> to support, and getting bits in a piece at a time is probably a good idea.
>
> On Wed, Mar 20, 2019 at 05:36:32PM +0000, Jean-Philippe Brucker wrote:
>> When removing a mapping from a domain, we need to send an invalidation to
>> all devices that might have stored it in their Address Translation Cache
>> (ATC). In addition when updating the context descriptor of a live domain,
>> we'll need to send invalidations for all devices attached to it.
>>
>> Maintain a list of devices in each domain, protected by a spinlock. It is
>> updated every time we attach or detach devices to and from domains.
>>
>> It needs to be a spinlock because we'll invalidate ATC entries from
>> within hardirq-safe contexts, but it may be possible to relax the read
>> side with RCU later.
>>
>> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
>> ---
>> drivers/iommu/arm-smmu-v3.c | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
>> index d3880010c6cf..66a29c113dbc 100644
>> --- a/drivers/iommu/arm-smmu-v3.c
>> +++ b/drivers/iommu/arm-smmu-v3.c
>> @@ -594,6 +594,11 @@ struct arm_smmu_device {
>> struct arm_smmu_master_data {
>> struct arm_smmu_device *smmu;
>> struct arm_smmu_strtab_ent ste;
>> +
>> + struct arm_smmu_domain *domain;
>> + struct list_head domain_head;
>> +
>> + struct device *dev;
>> };
>>
>> /* SMMU private data for an IOMMU domain */
>> @@ -618,6 +623,9 @@ struct arm_smmu_domain {
>> };
>>
>> struct iommu_domain domain;
>> +
>> + struct list_head devices;
>> + spinlock_t devices_lock;
>> };
>>
>> struct arm_smmu_option_prop {
>> @@ -1493,6 +1501,9 @@ static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
>> }
>>
>> mutex_init(&smmu_domain->init_mutex);
>> + INIT_LIST_HEAD(&smmu_domain->devices);
>> + spin_lock_init(&smmu_domain->devices_lock);
>
> I'm wondering whether we can't take this a bit further and re-organise the
> data structures to make this a little simpler overall. Something along the
> lines of:
>
> struct arm_smmu_master_data {
> struct list_head list; // masters in the same domain
> struct arm_smmu_device *smmu;
> unsigned int num_sids;
> u32 *sids; // Points into fwspec
> struct arm_smmu_domain *domain; // NULL -> !assigned
> };
>
> and then just add a list_head into struct arm_smmu_domain to track the
> masters that have been attached (if you're feeling brave, you could put
> this into the s1_cfg).
I'm not sure about that last bit, shouldn't the list of masters apply to
both s1 and s2?
>
> The ATC invalidation logic would then be:
>
> - Detaching a device: walk over the sids from the master data
> - Unmapping a range from a domain: walk over the attached masters
>
> I think this would also allow us to remove struct arm_smmu_strtab_ent
> completely.
Makes sense, it does work and simplifies the structures. It makes the
PASID and PRI patches slightly nicer as well. I'll resend once my tests
complete.
Thanks,
Jean
>
> Dunno: this is one of the those things where you really have to try it
> to figure out why it doesn't work...
>
> Will
> _______________________________________________
> iommu mailing list
> iommu@lists.linux-foundation.org
> https://lists.linuxfoundation.org/mailman/listinfo/iommu
>
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next prev parent reply other threads:[~2019-04-05 16:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-20 17:36 [PATCH 0/4] Add PCI ATS support to Arm SMMUv3 Jean-Philippe Brucker
2019-03-20 17:36 ` [PATCH 1/4] ACPI/IORT: Check ATS capability in root complex nodes Jean-Philippe Brucker
2019-03-21 16:00 ` Sinan Kaya
2019-03-25 15:02 ` Jean-Philippe Brucker
2019-03-20 17:36 ` [PATCH 2/4] iommu/arm-smmu-v3: Link domains and devices Jean-Philippe Brucker
2019-04-04 14:39 ` Will Deacon
2019-04-05 16:35 ` Jean-Philippe Brucker [this message]
2019-04-05 16:39 ` Will Deacon
2019-04-05 18:07 ` Jean-Philippe Brucker
2019-03-20 17:36 ` [PATCH 3/4] iommu/arm-smmu-v3: Add support for PCI ATS Jean-Philippe Brucker
2019-03-21 15:52 ` Sinan Kaya
2019-03-25 15:01 ` Jean-Philippe Brucker
2019-03-20 17:36 ` [PATCH 4/4] iommu/arm-smmu-v3: Disable tagged pointers Jean-Philippe Brucker
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