From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E26DAC4707F for ; Tue, 25 May 2021 22:50:37 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 69690610A8 for ; Tue, 25 May 2021 22:50:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 69690610A8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tyfPIcoxzg30RyeE4RXgiFZgydYzWcwhC+oETIY/Q5M=; b=43PH+P/fv7zBra 3UlCAT2otBXXziIv9G9Isws8oXTE2fUsaQzhX1uw06s6dBm6d3NhNO04y6l4p2eNHQ2r8sFDuKBUX KElSP0dXs+PISjjJn8uFZUG6JY2neuh7DT1yoNO8EJsd9hEvZOQrO1irhvzlQ0Ab78cKmiVSA6rCT 98Y2oo8PuXzBDpwIn1wnMiZc/UwWMABTQe1ZbZalLRSIUnCSXbEUpwkWx4iX+m6PySJvb2z2jDOpX jd+exs2/w0sMgdiUye8lhGlYhRX5aKa+4sk4BbGjDti1wsDNEqAx5GU41R/jp/aEzeP7SiD1WEX1i R/L/V5NpOrfbYkGf52EQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1llfrO-008vQq-3r; Tue, 25 May 2021 22:49:14 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1llfrI-008vNE-J4; Tue, 25 May 2021 22:49:10 +0000 Received: from ip5f5aa64a.dynamic.kabel-deutschland.de ([95.90.166.74] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1llfrD-0006yi-3J; Wed, 26 May 2021 00:49:03 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Ezequiel Garcia , Mauro Carvalho Chehab , Rob Herring , Philipp Zabel , Lee Jones , Greg Kroah-Hartman , linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Alex Bee Cc: Alex Bee , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH 04/10] media: hantro: add support for Rockchip RK3066 Date: Wed, 26 May 2021 00:49:02 +0200 Message-ID: <3178385.3VsfAaAtOV@diego> In-Reply-To: <20210525152225.154302-5-knaerzche@gmail.com> References: <20210525152225.154302-1-knaerzche@gmail.com> <20210525152225.154302-5-knaerzche@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210525_154908_788376_4C116165 X-CRM114-Status: GOOD ( 30.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Am Dienstag, 25. Mai 2021, 17:22:19 CEST schrieb Alex Bee: > RK3066's VPU IP block is the predecessor from what RK3288 has. > The hardware differences are: > - supports decoding frame sizes up to 1920x1088 only > - doesn't have the 'G1_REG_SOFT_RESET' register > (requires another .reset callback for hantro_codec_ops, > since writing this register will result in non-working > IP block) > - has one ACLK/HCLK per vdpu/vepu > - ACLKs can be clocked up to 300 MHz only > - no MMU > (no changes required: CMA will be transparently used) > > Add a new RK3066 variant which reflect this differences. This variant > can be used for RK3188 as well. > > Signed-off-by: Alex Bee > --- > drivers/staging/media/hantro/hantro_drv.c | 1 + > drivers/staging/media/hantro/hantro_hw.h | 1 + > drivers/staging/media/hantro/rk3288_vpu_hw.c | 116 +++++++++++++++++++ > 3 files changed, 118 insertions(+) > > diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c > index 2f6b01c7a6a0..38ea7b24036e 100644 > --- a/drivers/staging/media/hantro/hantro_drv.c > +++ b/drivers/staging/media/hantro/hantro_drv.c > @@ -489,6 +489,7 @@ static const struct of_device_id of_hantro_match[] = { > { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, > { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, }, > { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, > + { .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, }, NIT: "someone" should introduce a separate patch ordering that list ;-) > #endif > #ifdef CONFIG_VIDEO_HANTRO_IMX8M > { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, > diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h > index 3d8b53567f16..de2bc367a15a 100644 > --- a/drivers/staging/media/hantro/hantro_hw.h > +++ b/drivers/staging/media/hantro/hantro_hw.h > @@ -163,6 +163,7 @@ enum hantro_enc_fmt { > extern const struct hantro_variant rk3399_vpu_variant; > extern const struct hantro_variant rk3328_vpu_variant; > extern const struct hantro_variant rk3288_vpu_variant; > +extern const struct hantro_variant rk3066_vpu_variant; > extern const struct hantro_variant imx8mq_vpu_variant; > extern const struct hantro_variant sama5d4_vdec_variant; > > diff --git a/drivers/staging/media/hantro/rk3288_vpu_hw.c b/drivers/staging/media/hantro/rk3288_vpu_hw.c > index fefd45269e52..29805c4bd92f 100644 > --- a/drivers/staging/media/hantro/rk3288_vpu_hw.c > +++ b/drivers/staging/media/hantro/rk3288_vpu_hw.c > @@ -10,8 +10,10 @@ > > #include "hantro.h" > #include "hantro_jpeg.h" > +#include "hantro_g1_regs.h" > #include "hantro_h1_regs.h" > > +#define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) > #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) > > /* > @@ -62,6 +64,52 @@ static const struct hantro_fmt rk3288_vpu_postproc_fmts[] = { > }, > }; > > +static const struct hantro_fmt rk3066_vpu_dec_fmts[] = { > + { > + .fourcc = V4L2_PIX_FMT_NV12, > + .codec_mode = HANTRO_MODE_NONE, > + }, > + { > + .fourcc = V4L2_PIX_FMT_H264_SLICE, > + .codec_mode = HANTRO_MODE_H264_DEC, > + .max_depth = 2, > + .frmsize = { > + .min_width = 48, > + .max_width = 1920, > + .step_width = MB_DIM, > + .min_height = 48, > + .max_height = 1088, > + .step_height = MB_DIM, > + }, > + }, > + { > + .fourcc = V4L2_PIX_FMT_MPEG2_SLICE, > + .codec_mode = HANTRO_MODE_MPEG2_DEC, > + .max_depth = 2, > + .frmsize = { > + .min_width = 48, > + .max_width = 1920, > + .step_width = MB_DIM, > + .min_height = 48, > + .max_height = 1088, > + .step_height = MB_DIM, > + }, > + }, > + { > + .fourcc = V4L2_PIX_FMT_VP8_FRAME, > + .codec_mode = HANTRO_MODE_VP8_DEC, > + .max_depth = 2, > + .frmsize = { > + .min_width = 48, > + .max_width = 1920, > + .step_width = MB_DIM, > + .min_height = 48, > + .max_height = 1088, > + .step_height = MB_DIM, > + }, > + }, > +}; > + > static const struct hantro_fmt rk3288_vpu_dec_fmts[] = { > { > .fourcc = V4L2_PIX_FMT_NV12, > @@ -126,6 +174,14 @@ static irqreturn_t rk3288_vepu_irq(int irq, void *dev_id) > return IRQ_HANDLED; > } > > +static int rk3066_vpu_hw_init(struct hantro_dev *vpu) > +{ > + /* Bump ACLKs to max. possible freq. to improve performance. */ > + clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ); > + clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ); hmm, I don't think that line was supposed to be double? Heiko > + return 0; > +} > + > static int rk3288_vpu_hw_init(struct hantro_dev *vpu) > { > /* Bump ACLK to max. possible freq. to improve performance. */ > @@ -133,6 +189,14 @@ static int rk3288_vpu_hw_init(struct hantro_dev *vpu) > return 0; > } > > +static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) > +{ > + struct hantro_dev *vpu = ctx->dev; > + > + vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT); > + vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG); > +} > + > static void rk3288_vpu_enc_reset(struct hantro_ctx *ctx) > { > struct hantro_dev *vpu = ctx->dev; > @@ -145,6 +209,33 @@ static void rk3288_vpu_enc_reset(struct hantro_ctx *ctx) > /* > * Supported codec ops. > */ > +static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = { > + [HANTRO_MODE_JPEG_ENC] = { > + .run = hantro_h1_jpeg_enc_run, > + .reset = rk3288_vpu_enc_reset, > + .init = hantro_jpeg_enc_init, > + .done = hantro_jpeg_enc_done, > + .exit = hantro_jpeg_enc_exit, > + }, > + [HANTRO_MODE_H264_DEC] = { > + .run = hantro_g1_h264_dec_run, > + .reset = rk3066_vpu_dec_reset, > + .init = hantro_h264_dec_init, > + .exit = hantro_h264_dec_exit, > + }, > + [HANTRO_MODE_MPEG2_DEC] = { > + .run = hantro_g1_mpeg2_dec_run, > + .reset = rk3066_vpu_dec_reset, > + .init = hantro_mpeg2_dec_init, > + .exit = hantro_mpeg2_dec_exit, > + }, > + [HANTRO_MODE_VP8_DEC] = { > + .run = hantro_g1_vp8_dec_run, > + .reset = rk3066_vpu_dec_reset, > + .init = hantro_vp8_dec_init, > + .exit = hantro_vp8_dec_exit, > + }, > +}; > > static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = { > [HANTRO_MODE_JPEG_ENC] = { > @@ -183,10 +274,35 @@ static const struct hantro_irq rk3288_irqs[] = { > { "vdpu", hantro_g1_irq }, > }; > > +static const char * const rk3066_clk_names[] = { > + "aclk_vdpu", "hclk_vdpu", > + "aclk_vepu", "hclk_vepu" > +}; > + > static const char * const rk3288_clk_names[] = { > "aclk", "hclk" > }; > > +const struct hantro_variant rk3066_vpu_variant = { > + .enc_offset = 0x0, > + .enc_fmts = rk3288_vpu_enc_fmts, > + .num_enc_fmts = ARRAY_SIZE(rk3288_vpu_enc_fmts), > + .dec_offset = 0x400, > + .dec_fmts = rk3066_vpu_dec_fmts, > + .num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts), > + .postproc_fmts = rk3288_vpu_postproc_fmts, > + .num_postproc_fmts = ARRAY_SIZE(rk3288_vpu_postproc_fmts), > + .postproc_regs = &hantro_g1_postproc_regs, > + .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER | > + HANTRO_VP8_DECODER | HANTRO_H264_DECODER, > + .codec_ops = rk3066_vpu_codec_ops, > + .irqs = rk3288_irqs, > + .num_irqs = ARRAY_SIZE(rk3288_irqs), > + .init = rk3066_vpu_hw_init, > + .clk_names = rk3066_clk_names, > + .num_clocks = ARRAY_SIZE(rk3066_clk_names) > +}; > + > const struct hantro_variant rk3288_vpu_variant = { > .enc_offset = 0x0, > .enc_fmts = rk3288_vpu_enc_fmts, > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel