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Tue, 18 Jun 2019 09:37:59 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 18 Jun 2019 09:37:59 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 18 Jun 2019 09:37:59 -0500 Received: from [127.0.0.1] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x5IEbu2L008675; Tue, 18 Jun 2019 09:37:56 -0500 Subject: Re: [PATCH 3/6] arm64: dts: ti: Add Support for J721E SoC To: Nishanth Menon , Arnd Bergmann , Olof Johansson , Santosh Shilimkar , Will Deacon , Catalin Marinas , Greg Kroah-Hartman , Mark Rutland , Rob Herring References: <20190522161921.20750-1-nm@ti.com> <20190522161921.20750-4-nm@ti.com> From: Tero Kristo Message-ID: <327b6685-40fd-7333-e78e-af215f2d432b@ti.com> Date: Tue, 18 Jun 2019 17:37:55 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190522161921.20750-4-nm@ti.com> Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190618_073834_634063_35B8B33C X-CRM114-Status: GOOD ( 21.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Tony Lindgren , linux-kernel@vger.kernel.org, Russell King , linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 22/05/2019 19:19, Nishanth Menon wrote: > The J721E SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration to enable lower system costs > of automotive applications such as infotainment, cluster, premium > Audio, Gateway, industrial and a range of broad market applications. > This SoC is designed around reducing the system cost by eliminating > the need of an external system MCU and is targeted towards ASIL-B/C > certification/requirements in addition to allowing complex software > and system use-cases. > > Some highlights of this SoC are: > * Dual Cortex-A72s in a single cluster, three clusters of lockstep > capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), > C7x floating point Vector DSP, Two C66x floating point DSPs. > * 3D GPU PowerVR Rogue 8XE GE8430 > * Vision Processing Accelerator (VPAC) with image signal processor and Depth > and Motion Processing Accelerator (DMPAC) > * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual > PRUs and dual RTUs > * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and > up to two DPI interfaces. > * Integrated Ethernet switch supporting up to a total of 8 external ports in > addition to legacy Ethernet switch of up to 2 ports. > * System MMU (SMMU) Version 3.0 and advanced virtualisation > capabilities. > * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, > 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, > I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. > * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL > management. > * Configurable L3 Cache and IO-coherent architecture with high data throughput > capable distributed DMA architecture under NAVSS > * Centralized System Controller for Security, Power, and Resource > Management (DMSC) > > See J721E Technical Reference Manual (SPRUIL1, May 2019) > for further details: http://www.ti.com/lit/pdf/spruil1 > > Signed-off-by: Nishanth Menon > --- > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 202 ++++++++++++++++++ > .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 72 +++++++ > arch/arm64/boot/dts/ti/k3-j721e.dtsi | 176 +++++++++++++++ > 3 files changed, 450 insertions(+) > create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi > create mode 100644 arch/arm64/boot/dts/ti/k3-j721e.dtsi > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > new file mode 100644 > index 000000000000..d42912044a5d > --- /dev/null > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > +&cbass_mcu_wakeup { > + dmsc: dmsc@44083000 { > + compatible = "ti,k2g-sci"; > + ti,host-id = <12>; > + > + mbox-names = "rx", "tx"; > + > + mboxes= <&secure_proxy_main 11>, > + <&secure_proxy_main 13>; > + > + reg-names = "debug_messages"; > + reg = <0x00 0x44083000 0x0 0x1000>; > + > + k3_pds: power-controller { > + compatible = "ti,sci-pm-domain"; > + #power-domain-cells = <1>; > + }; > + > + k3_clks: clocks { > + compatible = "ti,k2g-sci-clk"; > + #clock-cells = <2>; > + ti,scan-clocks-from-dt; ti,scan-clocks-from-dt is an invalid DT property, it was NAK:ed a while back. The same functionality is now going to be used by default, so the property is not needed anyway. Fixed this locally by dropping the property. -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel