From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5454C5519F for ; Wed, 18 Nov 2020 08:59:49 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 18EAA221E9 for ; Wed, 18 Nov 2020 08:59:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="irCS/fuU"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="twZUd3Wz"; dkim=fail reason="signature verification failed" (1024-bit key) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="V6zkbJia" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 18EAA221E9 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Content-ID:In-Reply-To:References: Message-ID:Date:Subject:To:From:Reply-To:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=HUMKRcFttezNh3NnNgsUns/wiXpnmFZa7KsgY0/9Koo=; b=irCS/fuULbzrf5u5X/dgnpOSH I6JbIgAbn4Ede9CokApr0Ap4pmCF1KYQ4ucUv+fvFZy/h/H0tKpfY2GWhAr4gfnuZ1b0rmW6LhInp fZYrMNSnu3FSEke7okkvkdGaNLG61uYNpdIdjOKCu0xgpvINO+++Waxm1Y1uf76F2UTvGbIJWhWdW UgCCq0fwlDXg36ljNDfYccdPSCI4ROxXN3WBCWsoO4xykq6TzRDyIGh1KpYXHd/NtfQBS0YJvLlOY 0XdfadsaDorWQZQ85pUbaM4DYo15AoAHK+RRUyAkGIKu5bbu0G9MNC+WInE60k0qXAZaiLeXFdyb6 +jcNSrMzg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfJJ1-0005To-SC; Wed, 18 Nov 2020 08:59:12 +0000 Received: from esa1.microchip.iphmx.com ([68.232.147.91]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kfJIe-0005J7-GJ for linux-arm-kernel@lists.infradead.org; Wed, 18 Nov 2020 08:58:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1605689928; x=1637225928; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-id:content-transfer-encoding: mime-version; bh=wNH6dWwa/adS2pNA+hybt3c11A0A1UW76Jvh8B6vIJc=; b=twZUd3Wz2yytxwIVi0fJP/AH2V2tB0u/PAodRPXCV7Gr4IacY9RY92HI dz6D+K8scrSNLM99GNLOkY4/E7otqXlxWAcpbIFSTioyZWcKnnE7FXz5G cwgTK/NHwvmDj2WqA/FZLTfMN7ilthiVQIdBwCWdHn0jaj77KM6eb6j8J lcCVKQRWvUmOvqlj5Vks2Aw7akyqckYCU2ZnF2qZazGhSZp4X3ji7pIvN I5owHCAWhmjYtAk9WHO7YtscYl5zy7L+XvcYxiqGeV3mn7+I5BNms9poe TiCbLpzQS7YXLBYU8J3wRGkpb5p7kXj0cJ/aiW7o8tH0F2CkFMALl4NOb w==; IronPort-SDR: GEiDqWS4VrP7m6riMCoiBom5UzEHzF8/74nj0yq1XWh5yiPeAspJYy+mOjNy/zUbqHnWIq+xbY ZN/27mv6jk8KZ1WU23A9/jflG3W0NEVemK6cMgMncghVCBXjZCuGkbIDJ14gsxHQnNekgwaZlK Rk0i/gO8NxHd2CNceJZ+qbl50pyBe0J1Itj7Li7D6acPZfWyS1K7cSRTw/JMNhvLzI/m7tIxu1 6Wn94bStfWadV0FouUv+BQTNSAu1gjx3obbofoFU7mB6rTuv4zJfGWJ14nq1msFSJDT0QHw7tK 9aY= X-IronPort-AV: E=Sophos;i="5.77,486,1596524400"; d="scan'208";a="104002916" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Nov 2020 01:58:42 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3; Wed, 18 Nov 2020 01:58:42 -0700 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1979.3 via Frontend Transport; Wed, 18 Nov 2020 01:58:42 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=gQOJSskTw+sx3XPmRqw2asRO6qMWW2w+q2Z6xxgSJKBHCF85NluTq/Y3p7y89jlObhzgEzEvkGOXgamNivmupFjWNM63T4WC33zs/+lEZAOv7FcZKOqD4cihVXa6CbkI9BPQE7n5x4rosbVcpnzRf4NIZPq2OKg2r5F4exkAqBQx5fRBaldymY5G/9k5Aq5Ec+OJ4qnqOdv/EEsktlutuUtks+crBNtUzYdyE2FxGVfPFLhEph/gtSNoWLWsBcAfMjqCC1MU2i8eyGtVrmTMO45h5fDbvjySKYW6W0SydcIR0sSXuIMAkpmfOpjrud/OPavyyyacllyGt3fw71iimg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wNH6dWwa/adS2pNA+hybt3c11A0A1UW76Jvh8B6vIJc=; b=GXjflSOYV7oKkyUC9rOgSUN/O3mJv9F/KSZy+2RNsyR+B0mJUuYUZt0AV6JNWb/OKi3xVfksT3TBjZbJsg911+af9gxmlez2CfMUB5iTqWBy0M1eb5Y4TfEc2rdX7W5rspJzaJUEiIAs34KFfjNwVV4p4fgJgsVHPg/6FRu5ADPt8x4F2VD1clbQgiORzjvcCT/Ik/ap/XQ5EU5g6Ar4Qde8xlh7IpzVxaKBIOspldckdl6FCyCnMaUIr2exks/DflutxMaur9ZEIRbU9nWAY0MKblTwvJ4pdiFYALZ+6HP/I4WI6QEfxmUC4OK78lpLk9i8H9fgbFQm62pcPy+vBQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=microchip.com; dmarc=pass action=none header.from=microchip.com; dkim=pass header.d=microchip.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector2-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wNH6dWwa/adS2pNA+hybt3c11A0A1UW76Jvh8B6vIJc=; b=V6zkbJiaAZGFwjascXmNfC0opjG/Y72/H3K+h/NtzYgdwSxBpBp1z9fp7tcJorMPQMuM1gWn6sWhzev6GjlvepAYjjqQAG+j9QH8MS1EMInb7bpFnOEoWvVyO4gxaZ5Y6c8MzCDW6zSOA6+5+PpUOuTmA9tWBrnIMUZMnxDp99I= Received: from DM6PR11MB3420.namprd11.prod.outlook.com (20.177.218.95) by DM5PR1101MB2108.namprd11.prod.outlook.com (10.174.105.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3564.25; Wed, 18 Nov 2020 08:58:41 +0000 Received: from DM6PR11MB3420.namprd11.prod.outlook.com ([fe80::f983:dc6d:ad81:9e18]) by DM6PR11MB3420.namprd11.prod.outlook.com ([fe80::f983:dc6d:ad81:9e18%7]) with mapi id 15.20.3589.021; Wed, 18 Nov 2020 08:58:41 +0000 From: To: , , , , , Subject: Re: [PATCH v4 06/11] clk: at91: clk-sam9x60-pll: allow runtime changes for pll Thread-Topic: [PATCH v4 06/11] clk: at91: clk-sam9x60-pll: allow runtime changes for pll Thread-Index: AQHWvAsXdqHXVxqoU0quyuo4xeR8ew== Date: Wed, 18 Nov 2020 08:58:40 +0000 Message-ID: <354a80e9-d072-bd75-daa3-fa0f66c9415f@microchip.com> References: <1604655988-353-1-git-send-email-claudiu.beznea@microchip.com> <1604655988-353-7-git-send-email-claudiu.beznea@microchip.com> <160538849947.60232.12002724470272520124@swboyd.mtv.corp.google.com> <24d975ca-1942-5f7f-ae89-7b572f48812c@microchip.com> <160566417078.60232.18106288530854376790@swboyd.mtv.corp.google.com> In-Reply-To: <160566417078.60232.18106288530854376790@swboyd.mtv.corp.google.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; dmarc=none action=none header.from=microchip.com; x-originating-ip: [86.124.22.247] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 68033ac9-799c-471d-750e-08d88ba02558 x-ms-traffictypediagnostic: DM5PR1101MB2108: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-bypassexternaltag: True x-ms-oob-tlc-oobclassifiers: OLM:10000; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: 8rDd6l0ubreQz8r8utgvv9AJJGkUy6HNu1+3/CSiMogOoHEORZxbtE694dhqP/o1TvIQ0m8cveA1fh+xOQ4cBDbnuBe893e5tpQExvxgXxfs7Ohe8LFn+4TIzXSAyCFj5At6RRYJLKgrMjD1JYTqcnEmU+C9ya342t4eJQCqq6p//7YckepnfTlUaAiQ0xzmNeaKEIeeyqQFttdtwNU5+IiAJakGndaN1g32pgJvp1YPKTaGAGTMtEucN+z1M1iSKbRELpLK1grRGvLoydv16S2c4w2a/FYN0MH4KS7qp5iDJ0E1WVSZQMX3ZitAal1hFeXOTYzCZ1sjcewushe6OKf2TyLSlWjSYAO6h8WpCGCDS33TMyz3aoW/OEtqvFB9 x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DM6PR11MB3420.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(346002)(39860400002)(136003)(376002)(396003)(366004)(2906002)(54906003)(31696002)(6506007)(53546011)(36756003)(5660300002)(66946007)(4326008)(83380400001)(31686004)(4001150100001)(2616005)(478600001)(186003)(110136005)(316002)(8676002)(26005)(8936002)(6512007)(86362001)(6486002)(71200400001)(66446008)(66476007)(76116006)(66556008)(64756008)(91956017)(43740500002); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata: Yn8roq1vcGGJtdy2zy6Yp8l3ep3n/H/lmf94Tg90J57Yz6n9RKUp6yjysKyg/D3hovEzWjuadabN2wEpvFN/zMks5Z+Zz0XU/Tj/sjJ4uvijUEI6egXToxMFqW/sCzL+P06RHP6zJofiqKWzdeYdEJXnyK5LSlZ6aHcVk7+QLgetPdm2F6r4u5RJ17a7gBeNeXGk4qOULMmq774kApA5IGODqjwhaxFt1rR3QEniTB+OS/IuEDWxmZnc2RNxJ8OSrDFu0ikpKJ6Vgi2eqHz4Qxll+1BCuuwrVHgtgRd5V5BWRZRvn3GOsjdnz0FUwU4ZtCSWxmLD45RbyCarWY+u5eUMBtF+pYoT3lJ14/OVYYil2IQilYJysr42/zqKKOY4+BPlRWU3nSMt5Z0Wps7bJWZIkTxaiWAMN0GiST9X9PBM2N75VKUl14Nlm9vn3HlCjDSoNB+i3EiYixYCHRVPT/L2Q9/xyMUZPEw97TD0Qxxxp+Ot8KruzC9WG6nigr6hIrQs7OvMIyYiNOGJjxloc1PS/HtyJfZ4c+gH+BnN6A2cpO8JSPTOo+BqnK3ArFSrR8zq/9J4ZAPsRn8+tbMd9ozaJuY2FUYcz84K+Fg3ffb2twk1/REZquHssbPtpRt7y5lGwLCL1LqFYbzua/uKVMrHj1xahRf2gt1i268yTqR6YumZoyxupGxvud6wUmFjR7L8Da9LxW7vEzjzPSdG3kxkbVCJom6YHxpnAMKLRvkHuDuM158QlzCqOdSm5UhtQDTXnYw+U2ztG7lItlw3tnh2+Q7g1nP1FfNbB6ghTVbSgzNl8TpLRCovlKyMN/3shfc7kKzYjq2ttfBwRuc8HkWnHRiqHc3ZTBv9OaHF86c8pFApPeJkGJ6ggywdhwVnpVwGQU+cw+pGvlWtUH3C4g== Content-ID: <58134C7DBA12704CB9D4D9AA8148DEB7@namprd11.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB3420.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 68033ac9-799c-471d-750e-08d88ba02558 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Nov 2020 08:58:40.9648 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mszR1l55hosCRqxZdoCHBNqbdlsj/adpaN9NaXWeKKTT+TyVy+w5SH8+9Fc7+09SoxNV3gfpFnEShZSopJ7U2nnYH6FubUQEYCVEnixUdWM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1101MB2108 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201118_035849_158812_CF0DCDA7 X-CRM114-Status: GOOD ( 31.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eugen.Hristev@microchip.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 18.11.2020 03:49, Stephen Boyd wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Quoting Claudiu.Beznea@microchip.com (2020-11-16 03:24:54) >> >> >> On 14.11.2020 23:14, Stephen Boyd wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe >>> >>> Quoting Claudiu Beznea (2020-11-06 01:46:23) >>>> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c >>>> index 78f458a7b2ef..6fe5d8530a0c 100644 >>>> --- a/drivers/clk/at91/clk-sam9x60-pll.c >>>> +++ b/drivers/clk/at91/clk-sam9x60-pll.c >>>> @@ -225,8 +225,51 @@ static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate, >>>> unsigned long parent_rate) >>>> { >>>> struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw); >>>> + struct sam9x60_frac *frac = to_sam9x60_frac(core); >>>> + struct regmap *regmap = core->regmap; >>>> + unsigned long irqflags, clkflags = clk_hw_get_flags(hw); >>>> + unsigned int val, cfrac, cmul; >>>> + long ret; >>>> + >>>> + ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true); >>>> + if (ret <= 0 || (clkflags & CLK_SET_RATE_GATE)) >>> >>> Is this function being called when the clk is enabled and it has the >>> CLK_SET_RATE_GATE flag set? >> >> Yes, this function could be called when CLK_SET_RATE_GATE is set. >> On SAMA7G5 there are multiple PLL blocks of the same type. All these PLLs >> are controlled by clk-sam9x60-pll.c driver. One of this PLL block fed the >> CPU who's frequency could be changed at run time. At the same time there >> are PLLs that fed hardware block not glitch free aware or that we don't >> want to allow the rate change (this is the case of SAM9X60's CPU PLL, or >> the DDR PLL on SAMA7G5). >> >> I'm confused why this driver needs to check >>> this flag. >> >> Because we have multiple PLLs of the same type, some of them feed hardware >> blocks that are glitch free aware of these PLLs' frequencies changes, some >> feed hardware blocks that are not glitch free aware of PLLs' frequencies >> changes or for some of them we don't want the frequency changes at all. > > Can we have different clk_ops for the different types of PLLs? Sure! I'll switch to this way. Thank you for your feedback, Claudiu Beznea > It looks > like the flag is being used to overload this function to do different > things depending on how the flags are set. What happens if we decide to > change the semantics of this clk flag? How does it map to this driver? > Ideally this driver shouldn't need to worry about this flag, at least > not in this function, except to figure out if it should do something > different like not write the value to the hardware or something like > that. > > The flag indicates to the clk framework that this clk should be gated > when clk_set_rate() is called on it. The driver should be able to figure > out that the clk is disabled by reading the hardware here and checking > the enable state, or it could just have different clk_ops for the > different type of PLL and do something different without checking the > flag. Either way, checking the flag looks wrong. > >>>> - .c = 1, >>>> + .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, >>> >>> Please indicate why clks are critical. >> >> Sure! I'll do it in next version. I chose it like this because they are >> feeding critical parts of the system like CPU or memory. >> >>> Whenever the CLK_IS_CRITICAL flag >>> is used we should have a comment indicating why. >> >> I was not aware of this rule. I'll update the code accordingly. > > Sorry. I should put a document comment next to the flag. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel