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Wed, 11 Aug 2021 09:06:51 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 00:06:49 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Aug 2021 00:06:49 +0800 Message-ID: <35e543ebb1dd389a0530ec48ebca8298816a2378.camel@mediatek.com> Subject: Re: [PATCH v6 2/7] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 From: Jason-JH Lin To: Matthias Brugger , Rob Herring , Chun-Kuang Hu , "Philipp Zabel" , Enric Balletbo i Serra , CC: David Airlie , Daniel Vetter , "Fabien Parent" , , Yongqiang Niu , , , , , , , Date: Thu, 12 Aug 2021 00:06:49 +0800 In-Reply-To: <28cc4599-6eda-4784-3d8f-4570c9ab60e8@gmail.com> References: <20210805205226.24880-1-jason-jh.lin@mediatek.com> <20210805205226.24880-3-jason-jh.lin@mediatek.com> <28cc4599-6eda-4784-3d8f-4570c9ab60e8@gmail.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210811_090710_000044_ED843C38 X-CRM114-Status: GOOD ( 28.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Matthias, On Fri, 2021-08-06 at 13:28 +0200, Matthias Brugger wrote: > Hi Jason, > > On 05/08/2021 22:52, jason-jh.lin wrote: > > Add mt8195 vdosys0 clock driver name and routing table to > > the driver data of mtk-mmsys. > > > > I'd like to see the implementation of vdosys1 as well, to better > understand why > we need two compatibles. Do you mean I have to merge this patch and [1] into the same patch? or just add [1] at the same series? or just include [1] at commit message? [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210722094551.15255-10-nancy.lin@mediatek.com/ > > > Signed-off-by: jason-jh.lin > > --- > > This patch is base on [1] > > > > [1] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding > > https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210805171346.24249-2-jason-jh.lin@mediatek.com/__;!!CTRNKA9wMg0ARbw!21Mclcdx-qMIpoqPQOZd_-TuzoUfzzJ8UBC_RDzmvz5ISZQjfJIAhhJDKYBClDfOZb71$ > > > > Please add the binding description to this series. OK, I'll add the binding patch into this series. > > > --- > > drivers/soc/mediatek/mt8195-mmsys.h | 96 > > ++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.c | 11 +++ > > include/linux/soc/mediatek/mtk-mmsys.h | 9 +++ > > 3 files changed, 116 insertions(+) > > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h > > > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h > > b/drivers/soc/mediatek/mt8195-mmsys.h > > new file mode 100644 > > index 000000000000..9339a786ec5d > > --- /dev/null > > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > > @@ -0,0 +1,96 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > + > > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H > > +#define __SOC_MEDIATEK_MT8195_MMSYS_H > > + > > +#define MT8195_VDO0_OVL_MOUT_EN > > 0xf14 > > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 > > BIT(0) > > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 > > BIT(1) > > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) > > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 > > BIT(4) > > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 > > BIT(5) > > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) > > + > > +#define MT8195_VDO0_SEL_IN 0xf34 > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << > > 0) > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << > > 0) > > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << > > 0) > > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 > > (0 << 4) > > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << > > 4) > > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 > > (0 << 5) > > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << > > 5) > > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << > > 8) > > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT > > (1 << 8) > > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT > > (0 << 9) > > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << > > 12) > > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE > > (1 << 12) > > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << > > 12) > > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT > > (0 << 16) > > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 > > (1 << 16) > > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT > > (0 << 17) > > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << > > 17) > > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 > > (0 << 20) > > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE > > (1 << 20) > > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN > > (0 << 21) > > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 > > (1 << 21) > > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 > > (0 << 22) > > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE > > (1 << 22) > > + > > +#define MT8195_VDO0_SEL_OUT > > 0xf38 > > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << > > 0) > > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << > > 0) > > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << > > 1) > > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE > > (1 << 1) > > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << > > 1) > > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE > > (0 << 4) > > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 > > (1 << 4) > > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 > > (0 << 8) > > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << > > 8) > > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 > > (2 << 8) > > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 > > (3 << 8) > > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN > > (4 << 8) > > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN > > (0 << 11) > > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0 > > (1 << 11) > > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << > > 12) > > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << > > 12) > > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE > > (2 << 12) > > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << > > 16) > > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 > > (1 << 16) > > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << > > 16) > > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE > > (3 << 16) > > + > > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] > > = { > > + { > > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, > > + MT8195_VDO0_OVL_MOUT_EN, > > MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 > > Please update the struct to the new version that includes a mask > field. > OK, I'll add [2] before my patch and also test it on mt8195 SoC platform. [2] https://patchwork.kernel.org/project/linux-mediatek/patch/20210729070549.5514-1-linux@fw-web.de/ > Regards, > Matthias -- Regards, Jason-JH Lin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel