Re: [RFC PATCH] perf cs-etm: Handle valid-but-zero timestamps

From: James Clark <james.clark@arm.com>
To: Leo Yan <leo.yan@linaro.org>
Cc: coresight@lists.linaro.org, mathieu.poirier@linaro.org,
	al.grant@arm.com,  branislav.rankov@arm.com, denik@chromium.org,
	suzuki.poulose@arm.com, anshuman.khandual@arm.com,
	Mike Leach <mike.leach@linaro.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
	John Garry <john.garry@huawei.com>, Will Deacon <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH] perf cs-etm: Handle valid-but-zero timestamps
Date: Tue, 11 May 2021 13:00:14 +0300	[thread overview]
Message-ID: <35fbbead-167a-51d5-f781-a7b9890857b2@arm.com> (raw)
In-Reply-To: <20210511080504.GC8273@leoy-ThinkPad-X240s>

On 11/05/2021 11:05, Leo Yan wrote:
> On Mon, May 10, 2021 at 01:39:04PM +0800, Leo Yan wrote:
>> On Fri, May 07, 2021 at 01:02:35PM +0300, James Clark wrote:
>>>
>>>
>>> On 07/05/2021 12:58, James Clark wrote:
>>>> There is an intermittent issue on Trogdor devices that
>>>> results in all Coresight timestamps having a value of zero.
>>>
>>> I've attached a file here that has the issue. From the dump you 
>>> can see the zero timestamps:
>>>
>>>         Idx:69; ID:10;  I_TIMESTAMP : Timestamp.; Updated val = 0x0
>>>         Idx:71; ID:10;  I_ATOM_F1 : Atom format 1.; E
>>>         Idx:72; ID:10;  I_ADDR_S_IS0 : Address, Short, IS0.; Addr=0xFFFFFFE723C65824 ~[0x5824]
>>>
>>> This doesn't have an impact on decoding as they end up being
>>> decoded in file order as in with timeless mode.
>>
>> Just remind, as Mike has mentioned that if the timestamp is zero, it
>> means the hardware setting for timestamp is not enabled properly.  So
>> for system wide or per CPU mode tracing, it's better to double check
>> what's the reason the timestamp is not enabled properly.
>>
>> IIUC, this patch breaks the existed rational in the code.  Let's think
>> about there have 4 CPUs, every CPU has its own AUX trace buffer, and
>> when decode the trace data, it will use 4 queues to track the packets
>> and every queue has its timestamp.
>>
>>   CPU0: cs_etm_queue -> ... -> packet_queue->timestamp
>>   CPU1: cs_etm_queue -> ... -> packet_queue->timestamp
>>   CPU2: cs_etm_queue -> ... -> packet_queue->timestamp
>>   CPU3: cs_etm_queue -> ... -> packet_queue->timestamp
>>
>> The issue is if all CPUs' timestamp are zero, it's impossible to find
>> a way to synthesize samples in the right time order.
> 
> I saw Denis's replying for the hardware issue for timestamp, wander if
> can add a new option "--force-aux-ts-zero" to override the hardware
> timestamp issue.  Without the option "--force-aux-ts-zero", the
> developers still have chance to observe the failure case caused by the
> abnormal timestamps.
> 

Hi Leo,

Now that you mention arguments, I remembered that you already can force something like that
with --disable-order.

There is also a recent commit "perf intel-pt: Support Z itrace option for timeless decoding"
which introduces this option:

	@@ -869,6 +869,7 @@ The letters are:
	     	L	synthesize last branch entries on existing event records
	 	s	skip initial number of events
	 	q	quicker (less detailed) decoding
	+	Z	prefer to ignore timestamps (so-called "timeless" decoding)

I will investigate if these are more relevant to fix this issue.

Thanks
James

> Thanks,
> Leo
> 

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