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Mon, 28 Sep 2020 11:22:56 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 22AB0C433FE; Mon, 28 Sep 2020 11:22:56 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 48196C433CA; Mon, 28 Sep 2020 11:22:55 +0000 (UTC) MIME-Version: 1.0 Date: Mon, 28 Sep 2020 16:52:55 +0530 From: Sai Prakash Ranjan To: Suzuki K Poulose Subject: Re: [PATCH 2/2] coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register In-Reply-To: <0e0bc2fd-0449-35bc-882a-3b942a55fda4@arm.com> References: <19e06f26c1e4b0bf48d3971e2f1fb1af27da159a.1601222348.git.saiprakash.ranjan@codeaurora.org> <0e0bc2fd-0449-35bc-882a-3b942a55fda4@arm.com> Message-ID: <388adccec089823fcd6d009892ad95a1@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200928_072325_765901_598DAA29 X-CRM114-Status: GOOD ( 24.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mathieu.poirier@linaro.org, alexander.shishkin@linux.intel.com, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, swboyd@chromium.org, peterz@infradead.org, denik@google.com, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Suzuki, On 2020-09-28 16:35, Suzuki K Poulose wrote: > Hi Sai, > > On 09/27/2020 05:20 PM, Sai Prakash Ranjan wrote: >> In commit f188b5e76aae ("coresight: etm4x: Save/restore state >> across CPU low power states"), mistakenly TRCVMIDCCTLR1 register >> value was saved in trcvmidcctlr0 state variable which is used to >> store TRCVMIDCCTLR0 register value in etm4x_cpu_save() and then >> same value is written back to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1 >> in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state >> variable available for TRCVMIDCCTLR1, so use it. >> >> Fixes: 8b44fdfef6a2 ("coresight: etm4x: Allow etm4x to be built as a >> module") > > Why is this commit in question ? My bad sorry, I thought there are two commits which touch this hunk of code, but I see now that the module code just renamed the file, so this fixes tag is not required. > >> Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU >> low power states") > > I believe this is the right fixes tag. > Yes, I will resend with only this fixes tag. >> Signed-off-by: Sai Prakash Ranjan >> --- >> drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index de76d57850bc..abd706b216ac 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -1243,7 +1243,7 @@ static int etm4_cpu_save(struct etmv4_drvdata >> *drvdata) >> state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1); >> state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0); >> - state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR1); >> + state->trcvmidcctlr1 = readl(drvdata->base + TRCVMIDCCTLR1); >> state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR); >> @@ -1353,7 +1353,7 @@ static void etm4_cpu_restore(struct >> etmv4_drvdata *drvdata) >> writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1); >> writel_relaxed(state->trcvmidcctlr0, drvdata->base + >> TRCVMIDCCTLR0); >> - writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1); >> + writel_relaxed(state->trcvmidcctlr1, drvdata->base + TRCVMIDCCTLR1); >> > > Reviewed-by: Suzuki K Poulose Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel