From: "Song Bao Hua (Barry Song)" <song.bao.hua@hisilicon.com>
To: Tim Chen <tim.c.chen@linux.intel.com>,
"valentin.schneider@arm.com" <valentin.schneider@arm.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
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Jonathan Cameron <jonathan.cameron@huawei.com>,
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Cc: "Zengtao \(B\)" <prime.zeng@hisilicon.com>,
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"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [RFC PATCH v3 0/2] scheduler: expose the topology of clusters and add cluster scheduler
Date: Wed, 3 Feb 2021 11:32:32 +0000 [thread overview]
Message-ID: <38ce39d2d4754d76934bb07370eff48b@hisilicon.com> (raw)
In-Reply-To: <737932c9-846a-0a6b-08b8-e2d2d95b67ce@linux.intel.com>
> -----Original Message-----
> From: Tim Chen [mailto:tim.c.chen@linux.intel.com]
> Sent: Friday, January 8, 2021 12:17 PM
> To: Song Bao Hua (Barry Song) <song.bao.hua@hisilicon.com>;
> valentin.schneider@arm.com; catalin.marinas@arm.com; will@kernel.org;
> rjw@rjwysocki.net; vincent.guittot@linaro.org; lenb@kernel.org;
> gregkh@linuxfoundation.org; Jonathan Cameron <jonathan.cameron@huawei.com>;
> mingo@redhat.com; peterz@infradead.org; juri.lelli@redhat.com;
> dietmar.eggemann@arm.com; rostedt@goodmis.org; bsegall@google.com;
> mgorman@suse.de; mark.rutland@arm.com; sudeep.holla@arm.com;
> aubrey.li@linux.intel.com
> Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> linux-acpi@vger.kernel.org; linuxarm@openeuler.org; xuwei (O)
> <xuwei5@huawei.com>; Zengtao (B) <prime.zeng@hisilicon.com>; tiantao (H)
> <tiantao6@hisilicon.com>
> Subject: Re: [RFC PATCH v3 0/2] scheduler: expose the topology of clusters and
> add cluster scheduler
>
>
>
> On 1/6/21 12:30 AM, Barry Song wrote:
> > ARM64 server chip Kunpeng 920 has 6 clusters in each NUMA node, and each
> > cluster has 4 cpus. All clusters share L3 cache data while each cluster
> > has local L3 tag. On the other hand, each cluster will share some
> > internal system bus. This means cache is much more affine inside one cluster
> > than across clusters.
> >
> > +-----------------------------------+ +---------+
> > | +------+ +------+ +---------------------------+ |
> > | | CPU0 | | cpu1 | | +-----------+ | |
> > | +------+ +------+ | | | | |
> > | +----+ L3 | | |
> > | +------+ +------+ cluster | | tag | | |
> > | | CPU2 | | CPU3 | | | | | |
> > | +------+ +------+ | +-----------+ | |
> > | | | |
> > +-----------------------------------+ | |
> > +-----------------------------------+ | |
> > | +------+ +------+ +--------------------------+ |
> > | | | | | | +-----------+ | |
> > | +------+ +------+ | | | | |
> > | | | L3 | | |
> > | +------+ +------+ +----+ tag | | |
> > | | | | | | | | | |
> > | +------+ +------+ | +-----------+ | |
> > | | | |
> > +-----------------------------------+ | L3 |
> > | data |
> > +-----------------------------------+ | |
> > | +------+ +------+ | +-----------+ | |
> > | | | | | | | | | |
> > | +------+ +------+ +----+ L3 | | |
> > | | | tag | | |
> > | +------+ +------+ | | | | |
> > | | | | | ++ +-----------+ | |
> > | +------+ +------+ |---------------------------+ |
> > +-----------------------------------| | |
> > +-----------------------------------| | |
> > | +------+ +------+ +---------------------------+ |
> > | | | | | | +-----------+ | |
> > | +------+ +------+ | | | | |
> > | +----+ L3 | | |
> > | +------+ +------+ | | tag | | |
> > | | | | | | | | | |
> > | +------+ +------+ | +-----------+ | |
> > | | | |
> > +-----------------------------------+ | |
> > +-----------------------------------+ | |
> > | +------+ +------+ +--------------------------+ |
> > | | | | | | +-----------+ | |
> > | +------+ +------+ | | | | |
> >
> >
>
> There is a similar need for clustering in x86. Some x86 cores could share L2
> caches that
> is similar to the cluster in Kupeng 920 (e.g. on Jacobsville there are 6 clusters
> of 4 Atom cores, each cluster sharing a separate L2, and 24 cores sharing L3).
> Having a sched domain at the L2 cluster helps spread load among
> L2 domains. This will reduce L2 cache contention and help with
> performance for low to moderate load scenarios.
>
> The cluster detection mechanism will need
> to be based on L2 cache sharing in this case. I suggest making the
> cluster detection to be CPU architecture dependent so both ARM64 and x86 use
> cases
> can be accommodated.
>
> Attached below are two RFC patches for creating x86 L2
> cache sched domain, sans the idle cpu selection on wake up code. It is
> similar enough in concept to Barry's patch that we should have a
> single patchset that accommodates both use cases.
Hi Tim, Agreed on this.
hopefully the RFC v4 I am preparing will cover your case.
>
> Thanks.
>
> Tim
Thanks
Barry
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next prev parent reply other threads:[~2021-02-03 11:34 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-06 8:30 [RFC PATCH v3 0/2] scheduler: expose the topology of clusters and add cluster scheduler Barry Song
2021-01-06 8:30 ` [RFC PATCH v3 1/2] topology: Represent clusters of CPUs within a die Barry Song
2021-02-09 22:48 ` Masayoshi Mizuma
2021-01-06 8:30 ` [RFC PATCH v3 2/2] scheduler: add scheduler level for clusters Barry Song
2021-01-06 16:29 ` Vincent Guittot
2021-01-06 20:09 ` Song Bao Hua (Barry Song)
2021-01-07 23:16 ` [RFC PATCH v3 0/2] scheduler: expose the topology of clusters and add cluster scheduler Tim Chen
2021-01-08 15:12 ` Morten Rasmussen
2021-01-08 20:22 ` Tim Chen
2021-01-11 9:28 ` Morten Rasmussen
2021-01-12 11:00 ` Dietmar Eggemann
2021-01-25 10:50 ` Song Bao Hua (Barry Song)
2021-01-26 11:02 ` Dietmar Eggemann
2021-04-13 10:45 ` Song Bao Hua (Barry Song)
2021-04-13 19:00 ` Tim Chen
2021-01-08 21:30 ` Song Bao Hua (Barry Song)
2021-01-12 12:53 ` Dietmar Eggemann
2021-01-25 11:12 ` Song Bao Hua (Barry Song)
2021-02-03 11:32 ` Song Bao Hua (Barry Song) [this message]
2021-02-16 18:04 ` Tim Chen
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