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Sun, 11 Sep 2022 22:53:01 -0700 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Mon, 12 Sep 2022 13:12:27 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 12 Sep 2022 13:12:26 +0800 Message-ID: <3c67e742bdb06e55ba170a0a6dc79e6f6833c0e7.camel@mediatek.com> Subject: Re: [PATCH RESEND v3 6/9] drm/mediatek: Add gamma support different bank_size for other SoC From: CK Hu To: Jason-JH.Lin , Chun-Kuang Hu , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , AngeloGioacchino Del Regno CC: Rex-BC Chen , Singo Chang , , , , , , Date: Mon, 12 Sep 2022 13:12:26 +0800 In-Reply-To: <20220912013006.27541-7-jason-jh.lin@mediatek.com> References: <20220912013006.27541-1-jason-jh.lin@mediatek.com> <20220912013006.27541-7-jason-jh.lin@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220911_225310_725586_00383513 X-CRM114-Status: GOOD ( 20.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Jason: On Mon, 2022-09-12 at 09:30 +0800, Jason-JH.Lin wrote: > Add multiple bank support for mt8195. > If bank size is 0 which means no bank support. > > Signed-off-by: Jason-JH.Lin > --- > drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 45 +++++++++++++------ > ---- > 1 file changed, 26 insertions(+), 19 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c > b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c > index be82d15a5204..45da2b6206c8 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c > @@ -21,6 +21,7 @@ > #define GAMMA_LUT_EN BIT(1) > #define GAMMA_DITHERING BIT(2) > #define DISP_GAMMA_SIZE 0x0030 > +#define DISP_GAMMA_BANK 0x0100 > #define DISP_GAMMA_LUT 0x0700 > > #define LUT_10BIT_MASK 0x03ff > @@ -33,6 +34,7 @@ struct mtk_disp_gamma_data { > bool lut_diff; > u16 lut_size; > u8 lut_bits; > + u16 bank_size; > }; > > /* > @@ -75,9 +77,10 @@ void mtk_gamma_set_common(struct device *dev, void > __iomem *regs, struct drm_crt > struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); > bool lut_diff = false; > u16 lut_size = LUT_SIZE_DEFAULT; > + u16 bank_size = lut_size; > u8 lut_bits = LUT_BITS_DEFAULT; > u8 shift_bits; > - unsigned int i, reg; > + unsigned int i, j, reg, bank_num; > struct drm_color_lut *lut; > void __iomem *lut_base; > u32 word, mask; > @@ -87,8 +90,10 @@ void mtk_gamma_set_common(struct device *dev, void > __iomem *regs, struct drm_crt > lut_diff = gamma->data->lut_diff; > lut_size = gamma->data->lut_size; > lut_bits = gamma->data->lut_bits; > + bank_size = gamma->data->bank_size; > } > > + bank_num = lut_size / bank_size; > shift_bits = LUT_INPUT_BITS - lut_bits; > mask = GENMASK(lut_bits - 1, 0); > > @@ -98,25 +103,27 @@ void mtk_gamma_set_common(struct device *dev, > void __iomem *regs, struct drm_crt > writel(reg, regs + DISP_GAMMA_CFG); > lut_base = regs + DISP_GAMMA_LUT; > lut = (struct drm_color_lut *)state->gamma_lut->data; > - for (i = 0; i < lut_size; i++) { > - > - if (!lut_diff || (i % 2 == 0)) { > - word = (((lut[i].red >> shift_bits) & > mask) << 20) + > - (((lut[i].green >> shift_bits) > & mask) << 10) + > - ((lut[i].blue >> shift_bits) & > mask); > - } else { > - diff[0] = (lut[i].red >> shift_bits) - > - (lut[i - 1].red >> > shift_bits); > - diff[1] = (lut[i].green >> shift_bits) > - > - (lut[i - 1].green >> > shift_bits); > - diff[2] = (lut[i].blue >> shift_bits) - > - (lut[i - 1].blue >> > shift_bits); > - > - word = ((diff[0] & mask) << 20) + > - ((diff[1] & mask) << 10) + > - (diff[2] & mask); > + for (j = 0; j < bank_num; j++) { > + writel(j, regs + DISP_GAMMA_BANK); Does mt8173 and mt8183 has this register? If not, do not set this register in mt8173 and mt8183. Regards, CK > + for (i = 0; i < bank_size; i++) { > + if (!lut_diff || (i % 2 == 0)) { > + word = (((lut[i].red >> > shift_bits) & mask) << 20) + > + (((lut[i].green >> > shift_bits) & mask) << 10) + > + ((lut[i].blue >> > shift_bits) & mask); > + } else { > + diff[0] = (lut[i].red >> > shift_bits) - > + (lut[i - 1].red >> > shift_bits); > + diff[1] = (lut[i].green >> > shift_bits) - > + (lut[i - 1].green >> > shift_bits); > + diff[2] = (lut[i].blue >> > shift_bits) - > + (lut[i - 1].blue >> > shift_bits); > + > + word = ((diff[0] & mask) << 20) > + > + ((diff[1] & mask) << > 10) + > + (diff[2] & mask); > + } > + writel(word, (lut_base + i * 4)); > } > - writel(word, (lut_base + i * 4)); > } > } > } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel