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[68.111.84.250]) by smtp.gmail.com with ESMTPSA id n127sm6441841pfn.155.2020.09.10.12.07.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Sep 2020 12:08:03 -0700 (PDT) Subject: Re: [PATCH v11 04/11] PCI: brcmstb: Add suspend and resume pm_ops To: Jim Quinlan , Rob Herring References: <20200824193036.6033-1-james.quinlan@broadcom.com> <20200824193036.6033-5-james.quinlan@broadcom.com> <20200910155637.GA423872@bogus> From: Florian Fainelli Message-ID: <3c6a0acc-8966-fd38-1613-8da7bece81c7@gmail.com> Date: Thu, 10 Sep 2020 12:07:56 -0700 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Firefox/78.0 Thunderbird/78.2.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200910_150806_786804_D809C826 X-CRM114-Status: GOOD ( 24.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , Lorenzo Pieralisi , "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" , open list , Florian Fainelli , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , Bjorn Helgaas , Robin Murphy , Christoph Hellwig , Nicolas Saenz Julienne Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/10/2020 12:05 PM, Jim Quinlan wrote: > On Thu, Sep 10, 2020 at 2:50 PM Rob Herring wrote: >> >> On Thu, Sep 10, 2020 at 10:42 AM Jim Quinlan wrote: >>> >>> On Thu, Sep 10, 2020 at 11:56 AM Rob Herring wrote: >>>> >>>> On Mon, Aug 24, 2020 at 03:30:17PM -0400, Jim Quinlan wrote: >>>>> From: Jim Quinlan >>>>> >>>>> Broadcom Set-top (BrcmSTB) boards typically support S2, S3, and S5 suspend >>>>> and resume. Now the PCIe driver may do so as well. >>>>> >>>>> Signed-off-by: Jim Quinlan >>>>> Acked-by: Florian Fainelli >>>>> --- >>>>> drivers/pci/controller/pcie-brcmstb.c | 47 +++++++++++++++++++++++++++ >>>>> 1 file changed, 47 insertions(+) >>>>> >>>>> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c >>>>> index c2b3d2946a36..3d588ab7a6dd 100644 >>>>> --- a/drivers/pci/controller/pcie-brcmstb.c >>>>> +++ b/drivers/pci/controller/pcie-brcmstb.c >>>>> @@ -978,6 +978,47 @@ static void brcm_pcie_turn_off(struct brcm_pcie *pcie) >>>>> brcm_pcie_bridge_sw_init_set(pcie, 1); >>>>> } >>>>> >>>>> +static int brcm_pcie_suspend(struct device *dev) >>>>> +{ >>>>> + struct brcm_pcie *pcie = dev_get_drvdata(dev); >>>>> + >>>>> + brcm_pcie_turn_off(pcie); >>>>> + clk_disable_unprepare(pcie->clk); >>>>> + >>>>> + return 0; >>>>> +} >>>>> + >>>>> +static int brcm_pcie_resume(struct device *dev) >>>>> +{ >>>>> + struct brcm_pcie *pcie = dev_get_drvdata(dev); >>>>> + void __iomem *base; >>>>> + u32 tmp; >>>>> + int ret; >>>>> + >>>>> + base = pcie->base; >>>>> + clk_prepare_enable(pcie->clk); >>>>> + >>>>> + /* Take bridge out of reset so we can access the SERDES reg */ >>>>> + brcm_pcie_bridge_sw_init_set(pcie, 0); >>>>> + >>>>> + /* SERDES_IDDQ = 0 */ >>>>> + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); >>>>> + u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); >>>>> + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); >>>>> + >>>>> + /* wait for serdes to be stable */ >>>>> + udelay(100); >>>> >>>> Really needs to be a spinloop? >>>> >>>>> + >>>>> + ret = brcm_pcie_setup(pcie); >>>>> + if (ret) >>>>> + return ret; >>>>> + >>>>> + if (pcie->msi) >>>>> + brcm_msi_set_regs(pcie->msi); >>>>> + >>>>> + return 0; >>>>> +} >>>>> + >>>>> static void __brcm_pcie_remove(struct brcm_pcie *pcie) >>>>> { >>>>> brcm_msi_remove(pcie); >>>>> @@ -1087,12 +1128,18 @@ static int brcm_pcie_probe(struct platform_device *pdev) >>>>> >>>>> MODULE_DEVICE_TABLE(of, brcm_pcie_match); >>>>> >>>>> +static const struct dev_pm_ops brcm_pcie_pm_ops = { >>>>> + .suspend_noirq = brcm_pcie_suspend, >>>>> + .resume_noirq = brcm_pcie_resume, >>>> >>>> Why do you need interrupts disabled? There's 39 cases of .suspend_noirq >>>> and 1352 of .suspend in the tree. >>> >>> I will test switching this to suspend_late/resume_early. >> >> Why not just the 'regular' flavor suspend/resume? >> >> Rob > We must have our PCIe driver suspend last and resume first because our > current driver turns off/on the power for the EPs. Note that this > code isn't in the driver as we are still figuring out a way to make it > upstreamable. The suspend/resume ordering should be guaranteed by the Linux device driver model though if not, this is a bug that ought to be fixed. The PCI bridge sits at the top of the pci_device list and all EPs should be child devices, so the suspend order should be from EPs down to the bridge, and the resume the converse. -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel