From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B4A1C07E95 for ; Tue, 13 Jul 2021 07:28:48 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1C1E660E0B for ; Tue, 13 Jul 2021 07:28:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1C1E660E0B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:References:CC:To:From:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=NbzivRaVc6pKrDa/+Mtk5oBaLh89lq7ZhE9PqUdWIgs=; b=aZK4Vw0YfW3Vdqfnp/qE8lCxfr S80d2CD8y4qmzwdsG0jJp15k/Gm2mCQlmfiEQkK2jfy4/9EehyUmQHiXnDnux8C+BC7OokpZT69Xj DdoMIHpCmHQFumEZB0rhJedX+QzQ7JFdLxFFfy9MNsJ0yfeJ4FRZY8ZvjJvwOhpXG/SCW3V0G8Scq Zio+yROQVXCYgnC/FAgyP0uC7NI+NVOVFoJVhab6wQabXC/MtUb+YZuW78vQv0Gng4Q4WLysZjEcn qrodAdAEjMSD63iOE2tNUB6pKlQj1Qk7mUgIJTMIwpZcqEBHNoj/Uu4Q059r3FMoRyl0eF9ZFUWZ/ 9ty688mw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3Cp4-009Mt2-Rj; Tue, 13 Jul 2021 07:27:18 +0000 Received: from szxga01-in.huawei.com ([45.249.212.187]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m3Coz-009MrO-E7 for linux-arm-kernel@lists.infradead.org; Tue, 13 Jul 2021 07:27:15 +0000 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.55]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4GPBvP6gWQzbbpG; Tue, 13 Jul 2021 15:23:45 +0800 (CST) Received: from dggpemm500002.china.huawei.com (7.185.36.229) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 13 Jul 2021 15:27:02 +0800 Received: from [10.174.179.5] (10.174.179.5) by dggpemm500002.china.huawei.com (7.185.36.229) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 13 Jul 2021 15:27:01 +0800 Subject: Re: [PATCH net-next 1/3] arm64: barrier: add DGH macros to control memory accesses merging From: Xiongfeng Wang To: Will Deacon , Guangbin Huang CC: , , , , , , , , , , , References: <1624360271-17525-1-git-send-email-huangguangbin2@huawei.com> <1624360271-17525-2-git-send-email-huangguangbin2@huawei.com> <20210622121630.GC30757@willie-the-truck> <0c8f931b-9da8-ffb0-4b7c-7d291e9af8aa@huawei.com> Message-ID: <3ef9ca7d-e203-2041-2b6a-ed73c5e8e7b6@huawei.com> Date: Tue, 13 Jul 2021 15:27:01 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <0c8f931b-9da8-ffb0-4b7c-7d291e9af8aa@huawei.com> X-Originating-IP: [10.174.179.5] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To dggpemm500002.china.huawei.com (7.185.36.229) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210713_002713_992989_2647CF27 X-CRM114-Status: GOOD ( 24.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On 2021/6/29 19:11, Xiongfeng Wang wrote: > Hi Will, > > On 2021/6/22 20:16, Will Deacon wrote: >> On Tue, Jun 22, 2021 at 07:11:09PM +0800, Guangbin Huang wrote: >>> From: Xiongfeng Wang >>> >>> DGH prohibits merging memory accesses with Normal-NC or Device-GRE >>> attributes before the hint instruction with any memory accesses >>> appearing after the hint instruction. Provide macros to expose it to the >>> arch code. >> >> Hmm. >> >> The architecture states: >> >> | DGH is a hint instruction. A DGH instruction is not expected to be >> | performance optimal to merge memory accesses with Normal Non-cacheable >> | or Device-GRE attributes appearing in program order before the hint >> | instruction with any memory accesses appearing after the hint instruction >> | into a single memory transaction on an interconnect. >> >> which doesn't make a whole lot of sense to me, in all honesty. >> >>> Signed-off-by: Xiongfeng Wang >>> Signed-off-by: Cheng Jian >>> Signed-off-by: Yufeng Mo >>> --- >>> arch/arm64/include/asm/assembler.h | 7 +++++++ >>> arch/arm64/include/asm/barrier.h | 1 + >>> 2 files changed, 8 insertions(+) >>> >>> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h >>> index 8418c1bd8f04..d723899328bd 100644 >>> --- a/arch/arm64/include/asm/assembler.h >>> +++ b/arch/arm64/include/asm/assembler.h >>> @@ -90,6 +90,13 @@ >>> .endm >>> >>> /* >>> + * Data gathering hint >>> + */ >>> + .macro dgh >>> + hint #6 >>> + .endm >>> + >>> +/* >>> * RAS Error Synchronization barrier >>> */ >>> .macro esb >>> diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h >>> index 451e11e5fd23..02e1735706d2 100644 >>> --- a/arch/arm64/include/asm/barrier.h >>> +++ b/arch/arm64/include/asm/barrier.h >>> @@ -22,6 +22,7 @@ >>> #define dmb(opt) asm volatile("dmb " #opt : : : "memory") >>> #define dsb(opt) asm volatile("dsb " #opt : : : "memory") >>> >>> +#define dgh() asm volatile("hint #6" : : : "memory") >> >> Although I'm fine with this in arm64, I don't think this is the interface >> which drivers should be using. Instead, once we know what this instruction >> is supposed to do, we should look at exposing it as part of the I/O barriers >> and providing a NOP implementation for other architectures. That way, >> drivers can use it without having to have the #ifdef CONFIG_ARM64 stuff that >> you have in the later patches here. > > How about we adding a interface called flush_wc_writeX(), which can be used to > flush the write-combined buffers to the device immediately. > I found it has been disscussed in the below link, but it is unnessary in their > situation. > https://patchwork.ozlabs.org/project/netdev/patch/20200102180830.66676-3-liran.alon@oracle.com/ Do you have some suggestions on this problem ? How about we adding an interface called flush_wc_writeX() ? Thanks, Xiongfeng > > Thanks, > Xiongfeng > >> >> Will >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >> . >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel