From mboxrd@z Thu Jan 1 00:00:00 1970 From: sergei.shtylyov@cogentembedded.com (Sergei Shtylyov) Date: Tue, 12 Jul 2016 00:51:58 +0300 Subject: [PATCH 1/2] ARM: dts: r8a7792: add PLL1 divided by 2 clock In-Reply-To: <1529351.Fac5N2tKoF@wasted.cogentembedded.com> References: <1529351.Fac5N2tKoF@wasted.cogentembedded.com> Message-ID: <40786877.3MNoIeTZcz@wasted.cogentembedded.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Despite the QSPI clock has PLL1/VCOx1/4 clock as a parent, the latter hasn't been added to the R8A7792 device tree -- fix this overlook at last... Signed-off-by: Sergei Shtylyov --- arch/arm/boot/dts/r8a7792.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7792.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi +++ renesas/arch/arm/boot/dts/r8a7792.dtsi @@ -469,6 +469,13 @@ }; /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2 { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>;