Re: [PATCH v7 2/2] drivers/perf: hisi: Add driver for HiSilicon PCIe PMU

From: John Garry <john.garry@huawei.com>
To: Qi Liu <liuqi115@huawei.com>, <will@kernel.org>,
	<mark.rutland@arm.com>, <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <linuxarm@huawei.com>,
	<zhangshaokun@hisilicon.com>
Subject: Re: [PATCH v7 2/2] drivers/perf: hisi: Add driver for HiSilicon PCIe PMU
Date: Fri, 25 Jun 2021 16:53:35 +0100	[thread overview]
Message-ID: <485dcb90-01bc-766a-466a-f32563e2076f@huawei.com> (raw)
In-Reply-To: <1624532384-43002-3-git-send-email-liuqi115@huawei.com>

On 24/06/2021 11:59, Qi Liu wrote:
> +
> +/*
> + * Events with the "dl" suffix in their names count performance in DL layer,
> + * otherswise, events count performance in TL layer.
> + */
> +static struct attribute *hisi_pcie_pmu_events_attr[] = {
> +	HISI_PCIE_PMU_EVENT_ATTR(bw_rx_mwr, 0x010004),
> +	HISI_PCIE_PMU_EVENT_ATTR(bw_rx_mrd, 0x100005),
> +	HISI_PCIE_PMU_EVENT_ATTR(bw_tx_mwr, 0x010005),
> +	HISI_PCIE_PMU_EVENT_ATTR(bw_tx_mrd, 0x200004),
> +	HISI_PCIE_PMU_EVENT_ATTR(lat_rx_mwr, 0x000010),
> +	HISI_PCIE_PMU_EVENT_ATTR(lat_rx_mrd, 0x020010),
> +	HISI_PCIE_PMU_EVENT_ATTR(lat_tx_mrd, 0x000011),
> +	HISI_PCIE_PMU_EVENT_ATTR(bw_rx_dl, 0x010084),
> +	HISI_PCIE_PMU_EVENT_ATTR(bw_tx_dl, 0x030084),
> +	NULL
> +};
> +
> +static struct attribute_group hisi_pcie_pmu_events_group = {
> +	.name = "events",
> +	.attrs = hisi_pcie_pmu_events_attr,
> +};
> +
> +static struct attribute *hisi_pcie_pmu_format_attr[] = {
> +	HISI_PCIE_PMU_FORMAT_ATTR(event, "config:0-15"),
> +	HISI_PCIE_PMU_FORMAT_ATTR(subevent, "config:16-23"),
> +	HISI_PCIE_PMU_FORMAT_ATTR(thr_len, "config1:0-3"),
> +	HISI_PCIE_PMU_FORMAT_ATTR(thr_mode, "config1:4"),
> +	HISI_PCIE_PMU_FORMAT_ATTR(trig_len, "config1:5-8"),
> +	HISI_PCIE_PMU_FORMAT_ATTR(trig_mode, "config1:9"),
> +	HISI_PCIE_PMU_FORMAT_ATTR(port, "config2:0-15"),
> +	HISI_PCIE_PMU_FORMAT_ATTR(bdf, "config2:16-31"),
> +	NULL
> +};

I am just wondering how this now works.

So if the user programs the following:
./perf stat -v -e hisi_pcieX/lat_rx_mrd/

Then the value (incremented) in HISI_PCIE_CNT (I think that's the right 
one) is returned as the event count. But one would expect bandwidth from 
that event, while we only return here the delay cycles - how is the 
count in HISI_PCIE_CNT_EXT exposed, so userspace can do the calc for bw?

Thanks,
John

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