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Thu, 29 Apr 2021 10:50:20 -0700 Received: from fmsmsx610.amr.corp.intel.com ([10.18.126.90]) by fmsmsx610.amr.corp.intel.com ([10.18.126.90]) with mapi id 15.01.2106.013; Thu, 29 Apr 2021 10:50:20 -0700 From: "Luck, Tony" To: "Chatre, Reinette" , "tan.shaopeng@fujitsu.com" , "Yu, Fenghua" CC: "'linux-kernel@vger.kernel.org'" , "'linux-arm-kernel@lists.infradead.org'" , 'James Morse' , "misono.tomohiro@fujitsu.com" Subject: RE: About add an A64FX cache control function into resctrl Thread-Topic: About add an A64FX cache control function into resctrl Thread-Index: AQHXPR8AhIvM7pb1S52qTlM+pjp6RKrLxTbg Date: Thu, 29 Apr 2021 17:50:20 +0000 Message-ID: <49cdd0b707194148915e2efe2ab5d707@intel.com> References: <14ddf86b-89e1-ba26-b684-f3d5d5f8ade7@intel.com> In-Reply-To: <14ddf86b-89e1-ba26-b684-f3d5d5f8ade7@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.5.1.3 x-originating-ip: [10.22.254.132] MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210429_105023_515488_44950862 X-CRM114-Status: UNSURE ( 7.25 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org >>>> [Sector cache function] >>>> The sector cache function split cache into multiple sectors and >>>> control them separately. It is implemented on the L1D cache and >>>> L2 cache in the A64FX processor and can be controlled individually >>>> for L1D cache and L2 cache. A64FX has no L3 cache. Each L1D cache and >>>> L2 cache has 4 sectors. Which L1D sector is used is specified by the >>>> value of [57:56] bits of address, how many ways of sector are >>>> specified by the value of register (IMP_SCCR_L1_EL0). >>>> Which L2 sector is used is specified by the value of [56] bits of >>>> address, and how many ways of sector are specified by value of >>>> register (IMP_SCCR_ASSIGN_EL1, IMP_SCCR_SET0_L2_EL1, >>>> IMP_SCCR_SET1_L2_EL1). Are A64FX binaries position independent? I.e. could the OS reassign a running task to a different sector by remapping it to different virtual addresses during a context switch? Or is this a static property at task launch? -Tony _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel