From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DBE9C56202 for ; Thu, 26 Nov 2020 13:39:51 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D19CF2222C for ; Thu, 26 Nov 2020 13:39:50 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="y9S0IAHf" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D19CF2222C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=v0sI6RcihD2Qm/zSNh4buGFyInu39WYamI+0FXptLT8=; b=y9S0IAHfYUWPVFmNuYRTWXYVO XomU2LJdg9rr9yvdQAeWNxkpkt87hhaRQMogPnTXwergI+N662qzDj8eYGDLA2wWBP9fq+Ttg+LZC mE1ruBoNZ+FoakgUwE5IdXsOZkpSJT6XHdnAw/h4wppDOZ7ySB2BiNwGKM6MkWBfWGRCHQd6jEBL/ ctsh0MUdbbrcLY5jNLSFyDjQ82eCqG1HS4hRUbUrIwrYH8gGy/Fcg38QN7XecTat/yuZJFQBUIsED GYTGOJKPxUWkzF4KGjEccFnF97vDn2f5WhbnwCcE6KIEuX5akCxF84LD6a0H3eDVoOfXp8g2rNgxK rscGDO2Tg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kiHTi-0003KW-Me; Thu, 26 Nov 2020 13:38:30 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kiHTe-0003JW-Sj for linux-arm-kernel@lists.infradead.org; Thu, 26 Nov 2020 13:38:28 +0000 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4Chf2z68Skz74DG; Thu, 26 Nov 2020 21:38:03 +0800 (CST) Received: from [127.0.0.1] (10.65.95.32) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Thu, 26 Nov 2020 21:38:16 +0800 Subject: Re: [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM To: Suzuki K Poulose , , References: <1606138167-8076-1-git-send-email-liuqi115@huawei.com> From: Qi Liu Message-ID: <4acd7b82-74db-4df6-a7af-26f8434de45f@huawei.com> Date: Thu, 26 Nov 2020 21:38:15 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.7.1 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.65.95.32] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201126_083827_493908_DA6173C1 X-CRM114-Status: GOOD ( 22.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020/11/23 22:12, Suzuki K Poulose wrote: > Hi Qi > > Thanks for the changes. Mostly looks good to me, except for the > name of the call back. > > Hi Suzuki, ok, I'll send a new patch to change the name of call back. Thanks Qi > On 11/23/20 1:29 PM, Qi Liu wrote: >> The ETM device can't keep up with the core pipeline when cpu core >> is at full speed. This may cause overflow within core and its ETM. >> This is a common phenomenon on ETM devices. >> >> On HiSilicon Hip08 platform, a specific feature is added to set >> core pipeline. So commit rate can be reduced manually to avoid ETM >> overflow. >> >> Signed-off-by: Qi Liu > > >> --- >> Change since v1: >> - add CONFIG_ETM4X_IMPDEF_FEATURE and CONFIG_ETM4X_IMPDEF_HISILICON >> to keep specific feature off platforms which don't use it. >> Change since v2: >> - remove some unused variable. >> Change since v3: >> - use read/write_sysreg_s() to access register. >> >> drivers/hwtracing/coresight/Kconfig | 9 +++ >> drivers/hwtracing/coresight/coresight-etm4x-core.c | 84 ++++++++++++++++++++++ >> drivers/hwtracing/coresight/coresight-etm4x.h | 12 ++++ >> 3 files changed, 105 insertions(+) >> > >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >> index eefc737..1784975 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >> @@ -8,6 +8,7 @@ >> >> #include >> #include >> +#include >> #include "coresight-priv.h" >> >> /* >> @@ -203,6 +204,11 @@ >> /* Interpretation of resource numbers change at ETM v4.3 architecture */ >> #define ETM4X_ARCH_4V3 0x43 >> >> +enum etm_impdef_type { >> + ETM4_IMPDEF_HISI_CORE_COMMIT, >> + ETM4_IMPDEF_FEATURE_MAX, >> +}; >> + >> /** >> * struct etmv4_config - configuration information related to an ETMv4 >> * @mode: Controls various modes supported by this ETM. >> @@ -415,6 +421,7 @@ struct etmv4_save_state { >> * @state_needs_restore: True when there is context to restore after PM exit >> * @skip_power_up: Indicates if an implementation can skip powering up >> * the trace unit. >> + * @arch_features: Bitmap of arch features of etmv4 devices. >> */ >> struct etmv4_drvdata { >> void __iomem *base; >> @@ -463,6 +470,11 @@ struct etmv4_drvdata { >> struct etmv4_save_state *save_state; >> bool state_needs_restore; >> bool skip_power_up; >> + DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); >> +}; >> + >> +struct etm4_arch_features { >> + void (*set_commit)(bool enable); > > The set_commit is too hisilicon specific :-). Could we please rename > this to soemthing more generic. The callback for hisilicon etms, could still > be xx_commit". May be simply call it > > callback() ? > > or may be even > arch_callback() ? > > >> }; > > nit: This need not be part of the header file, as it is not used > outside the etm4x-core.c > > Suzuki > > . > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel