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From: Chanwoo Choi <cw00.choi@samsung.com>
To: Sylwester Nawrocki <s.nawrocki@samsung.com>,
	cwchoi00@gmail.com, Lukasz Luba <l.luba@partner.samsung.com>
Cc: devicetree <devicetree@vger.kernel.org>,
	linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
	Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
	Linux PM list <linux-pm@vger.kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Kyungmin Park <kyungmin.park@samsung.com>,
	Kukjin Kim <kgene@kernel.org>,
	MyungJoo Ham <myungjoo.ham@samsung.com>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Marek Szyprowski <m.szyprowski@samsung.com>
Subject: Re: [PATCH v4 4/8] drivers: devfreq: add DMC driver for Exynos5422
Date: Thu, 7 Mar 2019 10:10:15 +0900
Message-ID: <4bbc0f61-952e-bcdb-4645-2644a122ac99@samsung.com> (raw)
In-Reply-To: <94e169cf-4dc2-82ec-1385-852bc7853931@samsung.com>

Hi Sylwester,

On 19. 3. 6. 오후 10:44, Sylwester Nawrocki wrote:
> Hi,
> 
> On 2/3/19 13:23, Chanwoo Choi wrote:
> 
>> 2019년 2월 2일 (토) 오전 2:42, Lukasz Luba <l.luba@partner.samsung.com>님이 작성:
> 
>>> +/**
>>> + * exynos5_dmc_pause_on_switching() - Controls a pause feature in DMC
>>> + * @dmc:       device which is used for changing this feature
>>> + * @set:       a boolean state passing enable/disable request
>>> + *
>>> + * There is a need of pausing DREX DMC when divider or MUX in clock tree
>>> + * changes its configuration. In such situation access to the memory is blocked
>>> + * in DMC automatically. This feature is used when clock frequency change
>>> + * request appears and touches clock tree.
>>> + */
>>> +static int exynos5_dmc_pause_on_switching(struct exynos5_dmc *dmc, bool set)
>>
>> Don't need to make it as the separate function. It is only used on
>> probe() function.
> 
> It seems fine to me to have this functionality in a separate function, 
> it's self-contained and it's now pretty well documented.
> 
>>> +{
>>> +       unsigned int val;
>>> +
>>> +       val = readl(dmc->base_clk + DMC_PAUSE_CTRL);
>>> +       if (set)
>>> +               val |= DMC_PAUSE_ENABLE;
>>> +       else
>>> +               val &= ~DMC_PAUSE_ENABLE;
>>> +       writel(val, dmc->base_clk + DMC_PAUSE_CTRL);
>>
>> The dt-binding file doesn't explain the 'reg' property for 'base_clk'.
>> You are missing.
>> When I tried to find what are the base address, it is the register map
>> of clock-controller.
>> This driver accesed the register of clock controller without any
>> functions of CCF
>> (common clock framework). It is wrong.
>>
>> If you need to get the some information of clock, must have to use the CCF.
> We talked a little about this issue with Lukasz in person and it looks
> like there are some DMC related registers in the clock controller register 
> region, I'd say those registers are better handled by the DMC driver rather
> than the clocks controller driver. Moreover, we should avoid abusing clk API
> for not strictly clocks related functionality as it appears to be above.
> It might be more appropriate to add in the dmc DT node a phandle to a regmap
> exposed by the clock-controller node. It seems there will be even no single
> register that would be shared between the DMC and the clock controller.
> 

I agree to share the regmap instance of clock controller
with syscon_regmap_lookup_by_phandle() and then add the detailed
description about this to dt-binding documentation.


And,
This patch has the another quetion about the clocks in
exynos5_dmc_init_clks(). This functions used 'clk_set_parent'
to make the hierarchy between clocks. I think it is possible to make
the relation of clocks in DT by using the 'assigned-clocks'.

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

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  reply index

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com>
     [not found] ` <CGME20190201164718eucas1p1bca3a199d60e109e1da654d8afff2a47@eucas1p1.samsung.com>
2019-02-01 16:46   ` [PATCH v4 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Lukasz Luba
2019-02-13 21:07     ` Rob Herring
     [not found] ` <CGME20190201164719eucas1p2091c6d41a6cc21a3d36081daf4bc8267@eucas1p2.samsung.com>
2019-02-01 16:46   ` [PATCH v4 2/8] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
2019-02-03  9:56     ` Chanwoo Choi
2019-02-11 11:11       ` Lukasz Luba
2019-02-12  6:04         ` Chanwoo Choi
     [not found] ` <CGME20190201164719eucas1p106c8761eb4bff12a906b601a37bf58b5@eucas1p1.samsung.com>
2019-02-01 16:46   ` [PATCH v4 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
     [not found] ` <CGME20190201164720eucas1p13aac6550399d240b261a2cbe489d3dfc@eucas1p1.samsung.com>
2019-02-01 16:46   ` [PATCH v4 4/8] drivers: devfreq: add DMC driver for Exynos5422 Lukasz Luba
2019-02-03 12:23     ` Chanwoo Choi
2019-03-06 13:44       ` Sylwester Nawrocki
2019-03-07  1:10         ` Chanwoo Choi [this message]
2019-03-07  8:41           ` Sylwester Nawrocki
     [not found] ` <CGME20190201164720eucas1p1ae770f7981fa09016b69ca7265e820c7@eucas1p1.samsung.com>
2019-02-01 16:46   ` [PATCH v4 5/8] dt-bindings: devfreq: add Exynos5422 DMC device description Lukasz Luba
2019-02-03 12:28     ` Chanwoo Choi
     [not found] ` <CGME20190201164721eucas1p286976bab0cc9e06c2cf74a0eaa20144e@eucas1p2.samsung.com>
2019-02-01 16:46   ` [PATCH v4 6/8] DT: arm: exynos: add DMC device for exynos5422 Lukasz Luba
2019-02-08  8:14     ` Krzysztof Kozlowski
     [not found] ` <CGME20190201164722eucas1p1b619d939e0f93ddb9ee1af7306e7cf67@eucas1p1.samsung.com>
2019-02-01 16:46   ` [PATCH v4 7/8] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
     [not found] ` <CGME20190201164723eucas1p1ec009489584e1c85fd0d62270796e003@eucas1p1.samsung.com>
2019-02-01 16:46   ` [PATCH v4 8/8] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
2019-02-08  8:15     ` Krzysztof Kozlowski

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