From: "Trevor Wu (吳文良)" <Trevor.Wu@mediatek.com>
To: "p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>,
"angelogioacchino.delregno@collabora.com"
<angelogioacchino.delregno@collabora.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>,
"tiwai@suse.com" <tiwai@suse.com>,
"broonie@kernel.org" <broonie@kernel.org>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
Project_Global_Chrome_Upstream_Group
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v2 03/12] ASoC: mediatek: mt8188: support audsys clock
Date: Wed, 26 Oct 2022 04:10:30 +0000 [thread overview]
Message-ID: <500f80b1ac84101af482bdfcb46671d523d51068.camel@mediatek.com> (raw)
In-Reply-To: <473d67ed-198f-82c6-9f32-5827c1f8c852@collabora.com>
On Tue, 2022-10-25 at 12:18 +0200, AngeloGioacchino Del Regno wrote:
> Il 21/10/22 11:58, Trevor Wu (吳文良) ha scritto:
> > On Fri, 2022-10-21 at 10:41 +0200, AngeloGioacchino Del Regno
> > wrote:
> > > Il 21/10/22 10:27, Trevor Wu ha scritto:
> > > > Add mt8188 audio cg clock control. Audio clock gates are
> > > > registered
> > > > to CCF
> > > > for reference count and clock parent management.
> > > >
> > > > Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
> > > > ---
> > > > sound/soc/mediatek/mt8188/mt8188-audsys-clk.c | 206
> > > > ++++++++++++++++++
> > > > sound/soc/mediatek/mt8188/mt8188-audsys-clk.h | 15 ++
> > > > .../soc/mediatek/mt8188/mt8188-audsys-clkid.h | 83 +++++++
> > > > 3 files changed, 304 insertions(+)
> > > > create mode 100644 sound/soc/mediatek/mt8188/mt8188-audsys-
> > > > clk.c
> > > > create mode 100644 sound/soc/mediatek/mt8188/mt8188-audsys-
> > > > clk.h
> > > > create mode 100644 sound/soc/mediatek/mt8188/mt8188-audsys-
> > > > clkid.h
> > > >
> > > > diff --git a/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
> > > > b/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
> > > > new file mode 100644
> > > > index 000000000000..1f294231d4c2
> > > > --- /dev/null
> > > > +++ b/sound/soc/mediatek/mt8188/mt8188-audsys-clk.c
> > > > @@ -0,0 +1,206 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * mt8188-audsys-clk.c -- MediaTek 8188 audsys clock control
> > > > + *
> > > > + * Copyright (c) 2022 MediaTek Inc.
> > > > + * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
> > > > + */
> > > > +
> > > > +#include <linux/clk.h>
> > > > +#include <linux/clk-provider.h>
> > > > +#include <linux/clkdev.h>
> > > > +#include "mt8188-afe-common.h"
> > > > +#include "mt8188-audsys-clk.h"
> > > > +#include "mt8188-audsys-clkid.h"
> > > > +#include "mt8188-reg.h"
> > > > +
> > > > +struct afe_gate {
> > > > + int id;
> > > > + const char *name;
> > > > + const char *parent_name;
> > > > + int reg;
> > > > + u8 bit;
> > > > + const struct clk_ops *ops;
> > > > + unsigned long flags;
> > > > + u8 cg_flags;
> > > > +};
> > > > +
> > > > +#define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit,
> > > > _flags,
> > > > _cgflags) {\
> > > > + .id = _id,
> > > > \
> > > > + .name = _name,
> > > > \
> > > > + .parent_name = _parent,
> > > > \
> > > > + .reg = _reg,
> > > > \
> > > > + .bit = _bit,
> > > > \
> > > > + .flags = _flags,
> > > > \
> > > > + .cg_flags = _cgflags,
> > > > \
> > > > + }
> > > > +
> > > > +#define GATE_AFE(_id, _name, _parent, _reg, _bit)
> > > > \
> > > > + GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit,
> > > > \
> > > > + CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > > > CLK_GATE_SET_TO_DISABLE)
> > >
> > > Can you please explain what's the reason for CLK_IGNORE_UNUSED
> > > here?
> > > Maybe we can solve some issue that you're facing in a cleaner
> > > way.
> > >
> > > Regards,
> > > Angelo
> >
> > Hi Angelo,
> >
> > Because clk_disable_unused() calls clk_core_is_enabled(), register
> > access happens in is_enabled() ops.
> > At the moment, the power for register access is not enabled, so the
> > register read results in CPU hang.
> >
> > That's why I added CLK_IGNORE_UNUSED here, but it can't resolve all
> > issues. Actually, we met same problem when "cat
> > /sys/kernel/debug/clk/clk_summary" is used. We are still suffering
> > the
> > problem.
> >
> > I'm not sure if I can implement clk ops by myself, and exclude the
> > registration of is_enabled() ops.
> >
>
> Is the power for register access enabled with a power domain?
>
> Check drivers/clk/clk.c, grep for core->rpm_enabled.
>
> If you enable runtime PM before registering the clocks, and you
> register them
> with the right struct device, the clock API will enable power for you
> before
> trying to read the clock enable status.
>
> Regards,
> Angelo
>
Hi Angelo,
I tried the way in MT8195, but it caused circular lock problem.
Because mtcmos depends on some clocks, clk_bulk_prepare_enable is also
used in scpsys_power_on()[1].
If the clock also depends on the power domain, this results in the
circular lock problem.
That's why I don't bind the power domain with these clocks.
[1]
https://elixir.bootlin.com/linux/v6.1-rc2/source/drivers/soc/mediatek/mtk-pm-domains.c
Thanks,
Trevor
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next prev parent reply other threads:[~2022-10-26 4:22 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-21 8:27 [PATCH v2 00/12] ASoC: mediatek: Add support for MT8188 SoC Trevor Wu
2022-10-21 8:27 ` [PATCH v2 01/12] ASoC: mediatek: common: add SMC ops and SMC CMD Trevor Wu
2022-10-21 8:27 ` [PATCH v2 03/12] ASoC: mediatek: mt8188: support audsys clock Trevor Wu
2022-10-21 8:41 ` AngeloGioacchino Del Regno
2022-10-21 9:58 ` Trevor Wu (吳文良)
2022-10-25 10:18 ` AngeloGioacchino Del Regno
2022-10-26 4:10 ` Trevor Wu (吳文良) [this message]
2022-10-26 8:18 ` AngeloGioacchino Del Regno
2022-12-01 8:43 ` Trevor Wu (吳文良)
2022-12-01 9:42 ` AngeloGioacchino Del Regno
2022-10-21 8:27 ` [PATCH v2 04/12] ASoC: mediatek: mt8188: support adda in platform driver Trevor Wu
2022-10-21 8:41 ` AngeloGioacchino Del Regno
2022-10-21 8:27 ` [PATCH v2 05/12] ASoC: mediatek: mt8188: support etdm " Trevor Wu
2022-10-21 8:41 ` AngeloGioacchino Del Regno
2022-10-21 8:27 ` [PATCH v2 06/12] ASoC: mediatek: mt8188: support pcmif " Trevor Wu
2022-10-21 8:27 ` [PATCH v2 07/12] ASoC: mediatek: mt8188: support audio clock control Trevor Wu
2022-10-21 8:27 ` [PATCH v2 08/12] ASoC: mediatek: mt8188: add platform driver Trevor Wu
2022-10-21 8:27 ` [PATCH v2 09/12] ASoC: mediatek: mt8188: add control for timing select Trevor Wu
2022-10-21 8:27 ` [PATCH v2 10/12] dt-bindings: mediatek: mt8188: add audio afe document Trevor Wu
2022-10-24 18:33 ` Rob Herring
2022-10-31 7:11 ` Trevor Wu (吳文良)
2022-10-29 0:06 ` Krzysztof Kozlowski
2022-10-31 6:50 ` Trevor Wu (吳文良)
2022-10-21 8:27 ` [PATCH v2 11/12] ASoC: mediatek: mt8188: add machine driver with mt6359 Trevor Wu
2022-10-21 8:27 ` [PATCH v2 12/12] dt-bindings: mediatek: mt8188: add mt8188-mt6359 document Trevor Wu
2022-10-24 18:38 ` Rob Herring
2022-10-31 6:53 ` Trevor Wu (吳文良)
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