From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A278C4338F for ; Fri, 30 Jul 2021 11:45:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C284E6103B for ; Fri, 30 Jul 2021 11:45:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org C284E6103B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=collabora.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=FRBHOUh/2pVo0q6iZofZfawt514CKfDYA7z0ySZDv48=; b=zpmyYz7DBaJ5fQ9LMwUtUjWwA8 9zwyRqHRax9zBfjCRs0gGvZvY9t/US+weFBBOHfPRmE6e65Eh+AzIsVO6CgkFz3Qw2GYxdPV8Osu1 JznsfzHPXJjoMLuZTWBJodw6b+sV51d9fLIR0Yu82WmnbtIx+6vIWqaYnq7/MuZGdOT+xNhraRKCX 0N7tOLoTdX+UriYjBqe+l8/BmqMMIUSzRX/DQPOZfirmUmx0uW3APhh/FY6yDrrgzJ7Ls0wlfFW55 cmTXacyHdqz8k+5WBuETeughA+Pb7MTxqNgzRrWYbH/TogOaBXfAYFZ2krxZz8NzIUHCDM9xoSqVz qycDwGPA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m9Quf-008OY3-RA; Fri, 30 Jul 2021 11:42:50 +0000 Received: from bhuna.collabora.co.uk ([46.235.227.227]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m9Qtj-008O9Z-32; Fri, 30 Jul 2021 11:41:53 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 0929A1F41891 Subject: Re: [PATCH v5 2/6] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 To: "jason-jh.lin" , Rob Herring , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel , fshao@chromium.org Cc: David Airlie , Daniel Vetter , hsinyi@chromium.org, Yongqiang Niu , nancy.lin@mediatek.com, singo.chang@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org References: <20210729170737.21424-1-jason-jh.lin@mediatek.com> <20210729170737.21424-3-jason-jh.lin@mediatek.com> From: Enric Balletbo i Serra Message-ID: <51476e76-467c-6ade-69ba-09d861bee029@collabora.com> Date: Fri, 30 Jul 2021 13:41:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210729170737.21424-3-jason-jh.lin@mediatek.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210730_044151_423456_E2C24C84 X-CRM114-Status: GOOD ( 25.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Jason, Thank you for your patch. On 29/7/21 19:07, jason-jh.lin wrote: > Add mt8195 vdosys0 clock driver name and routing table to > the driver data of mtk-mmsys. > This patch is the one that is really introducing mt8195 mmsys support. It is a bit confusing sent the binding on another patchset. Please include [1] in this patchset so it's clear. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210722092624.14401-2-jason-jh.lin@mediatek.com/ > Signed-off-by: jason-jh.lin > --- > This patch is base on [1] > > [1]add mt8195 SoC DRM binding > - https://patchwork.kernel.org/project/linux-mediatek/list/?series=519597 > --- > drivers/soc/mediatek/mt8195-mmsys.h | 96 ++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 11 +++ > include/linux/soc/mediatek/mtk-mmsys.h | 9 +++ > 3 files changed, 116 insertions(+) > create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h > new file mode 100644 > index 000000000000..9339a786ec5d > --- /dev/null > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > @@ -0,0 +1,96 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H > +#define __SOC_MEDIATEK_MT8195_MMSYS_H > + > +#define MT8195_VDO0_OVL_MOUT_EN 0xf14 > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0) > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1) > +#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5) > +#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6) > + > +#define MT8195_VDO0_SEL_IN 0xf34 > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0) > +#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0) > +#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0) > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4) > +#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5) > +#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5) > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8) > +#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8) > +#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9) > +#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12) > +#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12) > +#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12) > +#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16) > +#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16) > +#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17) > +#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17) > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20) > +#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20) > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21) > +#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21) > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22) > +#define MT8195_SEL_IN_DISP_WDMA0_FROM_VPP_MERGE (1 << 22) > + > +#define MT8195_VDO0_SEL_OUT 0xf38 > +#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0) > +#define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0) > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1) > +#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1) > +#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1) > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4) > +#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4) > +#define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8) > +#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11) > +#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA0 (1 << 11) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12) > +#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16) > +#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16) > + > +static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = { If I understood correctly, in previous discussion you said that there will be two routing tables, one that is supposed to be for vdosys0 and another one vdosys1. The name here is too generic in my opinion, let's use a more specific name thinking in the future. > + { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, > + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 > + }, { > + DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1, > + MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 > + }, { > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 > + }, { > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0, > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_DSI0 > + }, { > + DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0, > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 > + }, { > + DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0, > + MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE > + } > +}; > + > +#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */ > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index 080660ef11bf..1fb241750897 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -13,6 +13,7 @@ > #include "mtk-mmsys.h" > #include "mt8167-mmsys.h" > #include "mt8183-mmsys.h" > +#include "mt8195-mmsys.h" > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .clk_driver = "clk-mt2701-mm", > @@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = { > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table), > }; > > +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = { > + .clk_driver = "clk-mt8195-vdo0", > + .routes = mmsys_mt8195_routing_table, > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), > +}; > + > struct mtk_mmsys { > void __iomem *regs; > const struct mtk_mmsys_driver_data *data; > @@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { > .compatible = "mediatek,mt8183-mmsys", > .data = &mt8183_mmsys_driver_data, > }, > + { > + .compatible = "mediatek,mt8195-vdosys0", > + .data = &mt8195_vdosys0_driver_data, > + }, > { } > }; > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h > index 2228bf6133da..01bedfb08094 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -39,6 +39,15 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_UFOE, > DDP_COMPONENT_WDMA0, > DDP_COMPONENT_WDMA1, > + DDP_COMPONENT_MERGE0, > + DDP_COMPONENT_MERGE1, > + DDP_COMPONENT_MERGE2, > + DDP_COMPONENT_MERGE3, > + DDP_COMPONENT_MERGE4, > + DDP_COMPONENT_MERGE5, > + DDP_COMPONENT_DSC0, > + DDP_COMPONENT_DSC1, > + DDP_COMPONENT_DP_INTF0, > DDP_COMPONENT_ID_MAX, > }; > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel