From mboxrd@z Thu Jan 1 00:00:00 1970 From: mperttunen@nvidia.com (Mikko Perttunen) Date: Thu, 31 Jul 2014 14:05:50 +0300 Subject: [PATCH 5/8] of: Add Tegra124 EMC bindings In-Reply-To: <53DA1EF0.7060207@nvidia.com> References: <1405088313-20048-1-git-send-email-mperttunen@nvidia.com> <1405088313-20048-6-git-send-email-mperttunen@nvidia.com> <53CD860B.7030800@wwwdotorg.org> <53CE9514.1050903@wwwdotorg.org> <53CEA093.6060106@wwwdotorg.org> <53D75B90.7050501@nvidia.com> <53D7C276.2080204@wwwdotorg.org> <53DA1EF0.7060207@nvidia.com> Message-ID: <53DA230E.7060903@nvidia.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 31/07/14 13:48, Mikko Perttunen wrote: >> >> I see that the TRM implies the whole 4-bit field is RAM code, rather >> than there being 2 separate 2-bit fields for RAM code and boot device >> code. Can you please file a bug against the TRM to document this >> correctly? (The details of which bits are which are visible on the >> Jetson TK1 schematics for example). > > Yes, I'll file a bug. On a closer look, the downstream kernel has been recently updated to consider the whole 4 bits the ram code. The relevant bug also has a comment mentioning that starting from T124, the whole 4 bits is considered the RAM code. > > - Mikko > -- > To unsubscribe from this list: send the line "unsubscribe linux-tegra" in > the body of a message to majordomo at vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >