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Sun, 01 Mar 2020 19:00:51 +0000 MIME-Version: 1.0 Date: Sun, 01 Mar 2020 19:00:51 +0000 From: Marc Zyngier To: Zenghui Yu Subject: Re: [PATCH v4 08/20] irqchip/gic-v4.1: Plumb get/set_irqchip_state SGI callbacks In-Reply-To: References: <20200214145736.18550-1-maz@kernel.org> <20200214145736.18550-9-maz@kernel.org> <4b7f71f1-5e7f-e6af-f47d-7ed0d3a8739f@huawei.com> <75597af0d2373ac4d92d8162a1338cbb@kernel.org> <19a7c193f0e4b97343e822a35f0911ed@kernel.org> <3d725ede-6631-59fb-1a10-9fb9890f3df6@huawei.com> Message-ID: <54c52057161f925c818446953050c951@kernel.org> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.10 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, lorenzo.pieralisi@arm.com, jason@lakedaemon.net, rrichter@marvell.com, tglx@linutronix.de, eric.auger@redhat.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200301_110054_467889_82AF38FF X-CRM114-Status: GOOD ( 13.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lorenzo Pieralisi , Jason Cooper , kvm@vger.kernel.org, Suzuki K Poulose , linux-kernel@vger.kernel.org, Eric Auger , Robert Richter , James Morse , Julien Thierry , Thomas Gleixner , kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-02-28 19:37, Marc Zyngier wrote: > On 2020-02-20 03:11, Zenghui Yu wrote: >> Do we really need to grab the vpe_lock for those which are belong to >> the same irqchip with its_vpe_set_affinity()? The IRQ core code should >> already ensure the mutual exclusion among them, wrong? > > I've been trying to think about that, but jet-lag keeps getting in the > way. > I empirically think that you are right, but I need to go and check the > various > code paths to be sure. Hopefully I'll have a bit more brain space next > week. So I slept on it and came back to my senses. The only case we actually need to deal with is when an affinity change impacts *another* interrupt. There is only two instances of this issue: - vLPIs have their *physical* affinity impacted by the affinity of the vPE. Their virtual affinity is of course unchanged, but the physical one becomes important with direct invalidation. Taking a per-VPE lock in such context should address the issue. - vSGIs have the exact same issue, plus the matter of requiring some *extra* one when reading the pending state, which requires a RMW on two different registers. This requires an extra per-RD lock. My original patch was stupidly complex, and the irq_desc lock is perfectly enough to deal with anything that only affects the interrupt state itself. GICv4 + direct invalidation for vLPIs breaks this by bypassing the serialization initially provided by the ITS, as the RD is completely out of band. The per-vPE lock brings back this serialization. I've updated the branch, which seems to run OK on D05. I still need to run the usual tests on the FVP model though. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel