From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F986C433F5 for ; Thu, 17 Mar 2022 13:12:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:CC:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9z45vK0c51FBkx9pMADzQoN3kA9h4yHvm5VB44w/q4s=; b=Av2bbI57bd2uxN 6MYE5Gehez3XfJfiutmfYtgQpmsVsiYRVL5VP6O2J3wf1v0eMaIrrl+yllIYeGR1YwwXslCA4vHW1 1ZFkJ7QQ0/BLJqBOmRbbaviB9Vtjai7W1ARcPFx58dSFn04e99TzBQttSUTD9WOA+OvjDUI9dy5h5 dvfk4tNj5SQlEKXvKTWLv4TVyRpzdBTW7Bbf7osFGpvrbhL98wOF7NYYERh69K3DVD2O8wwo/aemi loz+51F5v8ym7PNY7RVpRvIT5nYFS44kML57U5uu8AmN22nYHZ6whs24ujnmYgurB7Ofvmt8nTsWz ggylp9ZXVbqwadRt7WHA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUpuR-00GCHJ-Lh; Thu, 17 Mar 2022 13:11:19 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nUpuO-00GCGK-PE; Thu, 17 Mar 2022 13:11:18 +0000 X-UUID: 7d48e398bbb8466da8a5821ba37e69ed-20220317 X-UUID: 7d48e398bbb8466da8a5821ba37e69ed-20220317 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 367447800; Thu, 17 Mar 2022 06:11:11 -0700 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Mar 2022 06:01:09 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 17 Mar 2022 21:01:07 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 17 Mar 2022 21:01:07 +0800 Message-ID: <5c21b7c1606cf635123791c3e0c3a8a0cb8889c6.camel@mediatek.com> Subject: Re: [PATCH v15 04/22] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 From: Rex-BC Chen To: Nancy.Lin , Rob Herring , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel , , AngeloGioacchino Del Regno , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "jason-jh . lin" , Yongqiang Niu , , , , , , , , , Date: Thu, 17 Mar 2022 21:01:07 +0800 In-Reply-To: <20220311015506.11232-5-nancy.lin@mediatek.com> References: <20220311015506.11232-1-nancy.lin@mediatek.com> <20220311015506.11232-5-nancy.lin@mediatek.com> X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220317_061116_840805_DD27D114 X-CRM114-Status: GOOD ( 17.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 2022-03-11 at 09:54 +0800, Nancy.Lin wrote: > Add mt8195 vdosys1 clock driver name and routing table to > the driver data of mtk-mmsys. > > Signed-off-by: Nancy.Lin > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> Reviewed-by: Rex-BC Chen > --- > drivers/soc/mediatek/mt8195-mmsys.h | 136 > +++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 10 ++ > include/linux/soc/mediatek/mtk-mmsys.h | 2 + > 3 files changed, 148 insertions(+) > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h > b/drivers/soc/mediatek/mt8195-mmsys.h > index 24a3afe23bc8..369fb0aab56d 100644 > --- a/drivers/soc/mediatek/mt8195-mmsys.h > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > @@ -75,6 +75,70 @@ > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << > 16) > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE > (3 << 16) > > +#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04 > +#define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 > 1 > + > +#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08 > +#define MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 > 1 > + > +#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10 > +#define MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT > 0 > + > +#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14 > +#define MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT > 0 > + > +#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18 > +#define MT8195_MERGE4_SOUT_TO_DPI1_SEL > 2 > +#define MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL > 3 > + > +#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24 > +#define MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT > 1 > + > +#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28 > +#define MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT > 1 > + > +#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c > +#define MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT > 1 > + > +#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30 > +#define MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT > 1 > + > +#define MT8195_VDO1_MIXER_OUT_SOUT_SEL > 0xf34 > +#define MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL > 1 > + > +#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c > +#define MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 > 1 > + > +#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40 > +#define MT8195_SOUT_TO_MIXER_IN1_SEL > 1 > + > +#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44 > +#define MT8195_SOUT_TO_MIXER_IN2_SEL > 1 > + > +#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48 > +#define MT8195_SOUT_TO_MIXER_IN3_SEL > 1 > + > +#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c > +#define MT8195_SOUT_TO_MIXER_IN4_SEL > 1 > + > +#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN > 0xf50 > +#define MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT > 1 > + > +#define MT8195_VDO1_MIXER_IN1_SOUT_SEL > 0xf58 > +#define MT8195_MIXER_IN1_SOUT_TO_DISP_MIXER > 0 > + > +#define MT8195_VDO1_MIXER_IN2_SOUT_SEL > 0xf5c > +#define MT8195_MIXER_IN2_SOUT_TO_DISP_MIXER > 0 > + > +#define MT8195_VDO1_MIXER_IN3_SOUT_SEL > 0xf60 > +#define MT8195_MIXER_IN3_SOUT_TO_DISP_MIXER > 0 > + > +#define MT8195_VDO1_MIXER_IN4_SOUT_SEL > 0xf64 > +#define MT8195_MIXER_IN4_SOUT_TO_DISP_MIXER > 0 > + > +#define MT8195_VDO1_MIXER_SOUT_SEL_IN > 0xf68 > +#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER > 0 > + > static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = > { > { > DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0, > @@ -124,6 +188,78 @@ static const struct mtk_mmsys_routes > mmsys_mt8195_routing_table[] = { > DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0, > MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK, > MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0), > + MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0), > + MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0), > + MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0), > + MT8195_SOUT_TO_MIXER_IN1_SEL > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0), > + MT8195_SOUT_TO_MIXER_IN2_SEL > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0), > + MT8195_SOUT_TO_MIXER_IN3_SEL > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0), > + MT8195_SOUT_TO_MIXER_IN4_SEL > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0), > + MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0), > + MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0), > + MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0), > + MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0), > + MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0), > + MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER > + }, { > + DDP_COMPONENT_OVL_ADAPTOR, DDP_COMPONENT_MERGE5, > + MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0), > + MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT > + }, { > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, > + MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0), > + MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT > + }, { > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1, > + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), > + MT8195_MERGE4_SOUT_TO_DPI1_SEL > + }, { > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, > + MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0), > + MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT > + }, { > + DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1, > + MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0), > + MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL > } > }; > > diff --git a/drivers/soc/mediatek/mtk-mmsys.c > b/drivers/soc/mediatek/mtk-mmsys.c > index dc5c51f0ccc8..0b77624cf6ca 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -79,6 +79,12 @@ static const struct mtk_mmsys_driver_data > mt8195_vdosys0_driver_data = { > .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), > }; > > +static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data > = { > + .clk_driver = "clk-mt8195-vdo1", > + .routes = mmsys_mt8195_routing_table, > + .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table), > +}; > + > static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = > { > .clk_driver = "clk-mt8365-mm", > .routes = mt8365_mmsys_routing_table, > @@ -271,6 +277,10 @@ static const struct of_device_id > of_match_mtk_mmsys[] = { > .compatible = "mediatek,mt8195-vdosys0", > .data = &mt8195_vdosys0_driver_data, > }, > + { > + .compatible = "mediatek,mt8195-vdosys1", > + .data = &mt8195_vdosys1_driver_data, > + }, > { > .compatible = "mediatek,mt8365-mmsys", > .data = &mt8365_mmsys_driver_data, > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h > b/include/linux/soc/mediatek/mtk-mmsys.h > index 64c77c4a6c56..eaf7f7345519 100644 > --- a/include/linux/soc/mediatek/mtk-mmsys.h > +++ b/include/linux/soc/mediatek/mtk-mmsys.h > @@ -18,6 +18,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_COLOR1, > DDP_COMPONENT_DITHER, > DDP_COMPONENT_DP_INTF0, > + DDP_COMPONENT_DP_INTF1, > DDP_COMPONENT_DPI0, > DDP_COMPONENT_DPI1, > DDP_COMPONENT_DSC0, > @@ -39,6 +40,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OVL_2L0, > DDP_COMPONENT_OVL_2L1, > DDP_COMPONENT_OVL_2L2, > + DDP_COMPONENT_OVL_ADAPTOR, > DDP_COMPONENT_OVL1, > DDP_COMPONENT_POSTMASK0, > DDP_COMPONENT_PWM0, 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