From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B16F3C433EF for ; Fri, 3 Jun 2022 10:33:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KH49DtgURVhvIKjLi3Zud6/hyUKcCLpxn+79GdhsLRo=; b=P/dcVX0ihvAKAI dzKIrfuQOM7/8MXLD/WK2GsyXUrjXM05y4S5iArGO7/1IOh3cQWQA1F8ociuUrIZA9Wcd91wQEXp6 N9W1UR6VojHeva7fRW0ai8Nj19ZcgRI8RHa4KEMXIgpAH9sD33rdWOEI3v7AAflgNCr1MSoqJ4RGi sjfrpkmcyq2tz62ACDU2lG7ZznirbE5nZOKQLHpKzlng0xNSu2l6qmzISoF+q6+uahvqREkouyV1q LgMuLMWBoRyBz/GtL2/GRCI+wYUSwoLsDbK+f4gAi8ocpnczb3AnJT/zQh8ni5q3kc3bZkE5I3Uea EPyYmC+NJo9XE3Wl72mQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nx4b1-0074b8-3A; Fri, 03 Jun 2022 10:31:59 +0000 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nx4ax-0074aK-44; Fri, 03 Jun 2022 10:31:57 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id 81B83CE22D7; Fri, 3 Jun 2022 10:31:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 42F38C385A9; Fri, 3 Jun 2022 10:31:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1654252310; bh=uxKDQNP2ZIM59sJd/+dQG5xkTcM55eNMWdyr2X32D6g=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=o0hRM0IG/I22H9wIGay8MPt5gSxCJKew0MZ30/YttjF4KPdOUZAt9tWKlZOAztKOf Bc2u2bb6ZRKIEhtWoCREM2Ss+6zn+bVDKMqX1lpJL3CkCuIKZa2/OABcKljV3flWJ7 GUzT053LmCTaQePuKcPLfMtEz/K1InO0HxGIjH1DV8sYcThBtdkWfwanoJDdAqQiLi HKMQQrbTu/tltcWEHf6/1uRLp/T1RQmqfYtAANrjIzNe7jTxyWfCql6mEtSjmvWlgq XLMF025l17iff2AShrujEzMyBxWFGaz6ngHGwcnVqUwPUYsYZJvvzJaNEqyTrM7Jyx k4XpJmBUQrWMw== Message-ID: <5e57a1f3-1159-9277-5f8c-6ed0ad030a00@kernel.org> Date: Fri, 3 Jun 2022 13:31:44 +0300 MIME-Version: 1.0 Subject: Re: [PATCH v6 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings Content-Language: en-US To: Chanwoo Choi , Johnson Wang , krzk+dt@kernel.org, robh+dt@kernel.org, kyungmin.park@samsung.com Cc: khilman@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, jia-wei.chang@mediatek.com, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220527110036.8810-1-johnson.wang@mediatek.com> <20220527110036.8810-2-johnson.wang@mediatek.com> From: Georgi Djakov In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220603_033155_560103_260172A6 X-CRM114-Status: GOOD ( 20.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 3.06.22 3:39, Chanwoo Choi wrote: > Hi Georgi, > > If you agree this dt-bidning into .../bindings/interconnect, > I'll merge it. Could you please review it? > > On 5/27/22 8:00 PM, Johnson Wang wrote: >> Add devicetree binding of MediaTek CCI on MT8183 and MT8186. >> >> Signed-off-by: Jia-Wei Chang >> Signed-off-by: Johnson Wang >> Reviewed-by: Krzysztof Kozlowski >> Acked-by: Chanwoo Choi >> Reviewed-by: Chen-Yu Tsai Acked-by: Georgi Djakov Looks good to me. Thanks! BR, Georgi >> --- >> .../bindings/interconnect/mediatek,cci.yaml | 141 ++++++++++++++++++ >> MAINTAINERS | 1 + >> 2 files changed, 142 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml >> >> diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml >> new file mode 100644 >> index 000000000000..449c7c988229 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml >> @@ -0,0 +1,141 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: https://protect2.fireeye.com/v1/url?k=ad4ad61b-cc317c8c-ad4b5d54-74fe4860001d-01f34b7b1b45f9dd&q=1&e=81fe0992-6204-4794-b412-8ba4ca747e10&u=http%3A%2F%2Fdevicetree.org%2Fschemas%2Finterconnect%2Fmediatek%2Ccci.yaml%23 >> +$schema: https://protect2.fireeye.com/v1/url?k=a032f6c0-c1495c57-a0337d8f-74fe4860001d-83ce1b32f63b7f35&q=1&e=81fe0992-6204-4794-b412-8ba4ca747e10&u=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23 >> + >> +title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling >> + >> +maintainers: >> + - Jia-Wei Chang >> + - Johnson Wang >> + >> +description: | >> + MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by >> + MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in >> + hardware. It can also optimize the voltage to reduce the power consumption. >> + >> +properties: >> + compatible: >> + enum: >> + - mediatek,mt8183-cci >> + - mediatek,mt8186-cci >> + >> + clocks: >> + items: >> + - description: >> + The multiplexer for clock input of the bus. >> + - description: >> + A parent of "bus" clock which is used as an intermediate clock source >> + when the original clock source (PLL) is under transition and not >> + stable yet. >> + >> + clock-names: >> + items: >> + - const: cci >> + - const: intermediate >> + >> + operating-points-v2: true >> + opp-table: true >> + >> + proc-supply: >> + description: >> + Phandle of the regulator for CCI that provides the supply voltage. >> + >> + sram-supply: >> + description: >> + Phandle of the regulator for sram of CCI that provides the supply >> + voltage. When it is present, the implementation needs to do >> + "voltage tracking" to step by step scale up/down Vproc and Vsram to fit >> + SoC specific needs. When absent, the voltage scaling flow is handled by >> + hardware, hence no software "voltage tracking" is needed. >> + >> +required: >> + - compatible >> + - clocks >> + - clock-names >> + - operating-points-v2 >> + - proc-supply >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + cci: cci { >> + compatible = "mediatek,mt8183-cci"; >> + clocks = <&mcucfg CLK_MCU_BUS_SEL>, >> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; >> + clock-names = "cci", "intermediate"; >> + operating-points-v2 = <&cci_opp>; >> + proc-supply = <&mt6358_vproc12_reg>; >> + }; >> + >> + cci_opp: opp-table-cci { >> + compatible = "operating-points-v2"; >> + opp-shared; >> + opp2_00: opp-273000000 { >> + opp-hz = /bits/ 64 <273000000>; >> + opp-microvolt = <650000>; >> + }; >> + opp2_01: opp-338000000 { >> + opp-hz = /bits/ 64 <338000000>; >> + opp-microvolt = <687500>; >> + }; >> + opp2_02: opp-403000000 { >> + opp-hz = /bits/ 64 <403000000>; >> + opp-microvolt = <718750>; >> + }; >> + opp2_03: opp-463000000 { >> + opp-hz = /bits/ 64 <463000000>; >> + opp-microvolt = <756250>; >> + }; >> + opp2_04: opp-546000000 { >> + opp-hz = /bits/ 64 <546000000>; >> + opp-microvolt = <800000>; >> + }; >> + opp2_05: opp-624000000 { >> + opp-hz = /bits/ 64 <624000000>; >> + opp-microvolt = <818750>; >> + }; >> + opp2_06: opp-689000000 { >> + opp-hz = /bits/ 64 <689000000>; >> + opp-microvolt = <850000>; >> + }; >> + opp2_07: opp-767000000 { >> + opp-hz = /bits/ 64 <767000000>; >> + opp-microvolt = <868750>; >> + }; >> + opp2_08: opp-845000000 { >> + opp-hz = /bits/ 64 <845000000>; >> + opp-microvolt = <893750>; >> + }; >> + opp2_09: opp-871000000 { >> + opp-hz = /bits/ 64 <871000000>; >> + opp-microvolt = <906250>; >> + }; >> + opp2_10: opp-923000000 { >> + opp-hz = /bits/ 64 <923000000>; >> + opp-microvolt = <931250>; >> + }; >> + opp2_11: opp-962000000 { >> + opp-hz = /bits/ 64 <962000000>; >> + opp-microvolt = <943750>; >> + }; >> + opp2_12: opp-1027000000 { >> + opp-hz = /bits/ 64 <1027000000>; >> + opp-microvolt = <975000>; >> + }; >> + opp2_13: opp-1092000000 { >> + opp-hz = /bits/ 64 <1092000000>; >> + opp-microvolt = <1000000>; >> + }; >> + opp2_14: opp-1144000000 { >> + opp-hz = /bits/ 64 <1144000000>; >> + opp-microvolt = <1025000>; >> + }; >> + opp2_15: opp-1196000000 { >> + opp-hz = /bits/ 64 <1196000000>; >> + opp-microvolt = <1050000>; >> + }; >> + }; >> diff --git a/MAINTAINERS b/MAINTAINERS >> index 41c9c8f2b96d..7239f0e0c47b 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -5735,6 +5735,7 @@ L: linux-pm@vger.kernel.org >> S: Maintained >> T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git >> F: Documentation/devicetree/bindings/devfreq/ >> +F: Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml >> F: drivers/devfreq/ >> F: include/linux/devfreq.h >> F: include/trace/events/devfreq.h >> > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel