From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2561BC2D0A3 for ; Tue, 3 Nov 2020 12:45:38 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A296E22384 for ; Tue, 3 Nov 2020 12:45:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="VDzZHhk9" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A296E22384 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=HVPnY+SrXdysuSfyl4NtsVBVVJabz8A3MpTqWyWuZB0=; b=VDzZHhk9YVGBqj7fP8peYc9n2 mQgySBp89RYhKRsN2sR+P+osGB+PNS5g0kwvqXn943LLIN/IkROFXUY4WlvzK6ayZi+oQUfpcFhba NJixcY7XHahbZeGP3L3pRNs2GD86Y9l5sayU9iP+hbLFMFyvKBpyOTQjG1GiZxr0ue/x9odKhHgni fFlK1qO/sjDqquIBdTnlplyI3w5bpN8RvAW0kflNaruimeB1kUW93RWOOYfiRfm58w8Ig8B/ESxDO V+GrM6lvC/49kX1tUVkV7Q5V4TyoWgHikq8iXq2k+YMsyc65IfB//CU1bCEo3riaDbqiRucY9tmcP ID3K0+sUw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kZvgJ-000627-Ii; Tue, 03 Nov 2020 12:44:59 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kZvgE-00060c-9y for linux-arm-kernel@lists.infradead.org; Tue, 03 Nov 2020 12:44:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D9D84106F; Tue, 3 Nov 2020 04:44:50 -0800 (PST) Received: from [10.57.20.162] (unknown [10.57.20.162]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8EF663F718; Tue, 3 Nov 2020 04:44:49 -0800 (PST) Subject: Re: [PATCH v3] Coresight: etm4x: Add support for Self-hosted trace To: Jonathan Zhou , linux-arm-kernel@lists.infradead.org References: <1600396210-54196-1-git-send-email-jonathan.zhouwen@huawei.com> From: Suzuki K Poulose Message-ID: <64434152-10e3-dd8d-3493-e33713c64f1e@arm.com> Date: Tue, 3 Nov 2020 12:44:48 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <1600396210-54196-1-git-send-email-jonathan.zhouwen@huawei.com> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201103_074454_496115_139E1BAF X-CRM114-Status: GOOD ( 25.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shaokun Zhang , Catalin Marinas , Will Deacon , Mathieu Poirier Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Jonathan On 9/18/20 3:30 AM, Jonathan Zhou wrote: > ARMv8.4 architecture extension introduces ARMv8.4-Trace, Armv8.4 > Self-hosted Trace Extensions. It provides control of exception > levels and security states. Let's add this feature detection and > enable E1TRE and E0TRE in TRFCR_EL1 if Self-hosted Trace is > supported. > > Cc: Mathieu Poirier > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Suzuki K Poulose > Cc: Shaokun Zhang > Signed-off-by: Jonathan Zhou > --- > ChangeLog in v3: > * address Suzuki's comments > > arch/arm64/include/asm/sysreg.h | 17 +++++++++++++ > drivers/hwtracing/coresight/coresight-etm4x.c | 35 +++++++++++++++++++++++++++ > 2 files changed, 52 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 554a7e8ecb07..31b84a5fa35d 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -184,6 +184,22 @@ > > #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) > > +/* Trace Filter control EL1*/ > +#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) > +/* Trace Filter control EL2 */ > +#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1) Please keep the ordering of the definitions. > + > +/* Trace is allowed at EL0 */ > +#define TRFCR_EL1_E0TRE BIT(0) TRFCR_ELx_E0TRE ? > +/* Trace is allowed at EL1 */ > +#define TRFCR_EL1_E1TRE BIT(1) May be TRFCR_ELx_ELxTRE ? > +#define TRFCR_TS_SHIFT 5 > +#define TRFCR_TS_MASK GENMASK(6, 5) > +/* Virtual timestamp */ > +#define TRFCR_TS_VT (0x1UL << TRFCR_TS_SHIFT) > +/* Context idx is allowed at EL2 */ > +#define TRFCR_EL2_CX BIT(3) > + > #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) > #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) > #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) > @@ -772,6 +788,7 @@ > #define ID_AA64MMFR2_CNP_SHIFT 0 > > /* id_aa64dfr0 */ > +#define ID_AA64DFR0_SELF_HOSTED_SHIFT 40 Please stick to the architcted name for the field, TRACE_FILT > #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 > #define ID_AA64DFR0_PMSVER_SHIFT 32 > #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 96425e818fc2..82648a3c7a8e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -28,6 +28,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -785,6 +786,36 @@ static void etm4_init_arch_data(void *info) > CS_LOCK(drvdata->base); > } > > +static void etm4_init_sysctrl(void *info) > +{ > + u64 sys_trfcr_el1, dfr0; > + int trace_filt; > + > + dfr0 = read_sysreg(id_aa64dfr0_el1); > + > + trace_filt = cpuid_feature_extract_unsigned_field(dfr0, > + ID_AA64DFR0_SELF_HOSTED_SHIFT); > + if (trace_filt == 0x1) { > + sys_trfcr_el1 = read_sysreg_s(SYS_TRFCR_EL1); > + sys_trfcr_el1 &= (~TRFCR_TS_MASK); > + /* Enable EL1 & EL0 tracing. */ > + sys_trfcr_el1 |= TRFCR_EL1_E0TRE; > + sys_trfcr_el1 |= TRFCR_EL1_E1TRE; > + /* Use virtual timestamp */ > + sys_trfcr_el1 |= TRFCR_TS_VT; Could we simply do : u64 trcfr = (TRFCR_ELx_E0TRE | TRFCR_ELx_ExTRE | TRFCR_ELx_TS_VT) > + /* enable contextid_el2 and vmid tracing. */ > + if (is_kernel_in_hyp_mode()) > + sys_trfcr_el1 |= TRFCR_EL2_CX; > + /* > + * If pe is in EL2, we assume HCR_EL2.E2H == 1. Thus, accessing > + * TRFCR_EL1 is routed to TRFCR_EL2 and leave TRFCR_EL1 to be > + * configured by the kvm. > + */ > + write_sysreg_s(sys_trfcr_el1, SYS_TRFCR_EL1); > + isb(); > + } > +} > + > static void etm4_set_default_config(struct etmv4_config *config) > { > /* disable all events tracing */ > @@ -1504,6 +1535,10 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) > etm4_init_arch_data, drvdata, 1)) > dev_err(dev, "ETM arch init failed\n"); > > + if (smp_call_function_single(drvdata->cpu, > + etm4_init_sysctrl, drvdata, 1)) > + dev_err(dev, "ETM sysctrl init failed\n"); We could as well move this to etm4_init_arch_data(), which is called already on the CPU. Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel