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Tue, 18 Jun 2019 09:38:56 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 18 Jun 2019 09:38:55 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 18 Jun 2019 09:38:55 -0500 Received: from [127.0.0.1] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x5IEcpcb101103; Tue, 18 Jun 2019 09:38:52 -0500 Subject: Re: [PATCH 3/6] arm64: dts: ti: Add Support for J721E SoC To: Suman Anna , Nishanth Menon , Arnd Bergmann , Olof Johansson , Santosh Shilimkar , Will Deacon , Catalin Marinas , Greg Kroah-Hartman , Mark Rutland , Rob Herring References: <20190522161921.20750-1-nm@ti.com> <20190522161921.20750-4-nm@ti.com> From: Tero Kristo Message-ID: <665a246b-53ec-b10d-5fbb-840e950977a7@ti.com> Date: Tue, 18 Jun 2019 17:38:51 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190618_073914_177373_7D6EBB58 X-CRM114-Status: GOOD ( 17.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Tony Lindgren , linux-kernel@vger.kernel.org, Russell King , linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 07/06/2019 23:58, Suman Anna wrote: > Hi Nishanth, Tero, > > On 5/22/19 11:19 AM, Nishanth Menon wrote: >> The J721E SoC belongs to the K3 Multicore SoC architecture platform, >> providing advanced system integration to enable lower system costs >> of automotive applications such as infotainment, cluster, premium >> Audio, Gateway, industrial and a range of broad market applications. >> This SoC is designed around reducing the system cost by eliminating >> the need of an external system MCU and is targeted towards ASIL-B/C >> certification/requirements in addition to allowing complex software >> and system use-cases. >> >> Some highlights of this SoC are: >> * Dual Cortex-A72s in a single cluster, three clusters of lockstep >> capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), >> C7x floating point Vector DSP, Two C66x floating point DSPs. >> * 3D GPU PowerVR Rogue 8XE GE8430 >> * Vision Processing Accelerator (VPAC) with image signal processor and Depth >> and Motion Processing Accelerator (DMPAC) >> * Two Gigabit Industrial Communication Subsystems (ICSSG), each with dual >> PRUs and dual RTUs >> * Two CSI2.0 4L RX plus one CSI2.0 4L TX, one eDP/DP, One DSI Tx, and >> up to two DPI interfaces. >> * Integrated Ethernet switch supporting up to a total of 8 external ports in >> addition to legacy Ethernet switch of up to 2 ports. >> * System MMU (SMMU) Version 3.0 and advanced virtualisation >> capabilities. >> * Upto 4 PCIe-GEN3 controllers, 2 USB3.0 Dual-role device subsystems, >> 16 MCANs, 12 McASP, eMMC and SD, UFS, OSPI/HyperBus memory controller, QSPI, >> I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. >> * Two hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL >> management. >> * Configurable L3 Cache and IO-coherent architecture with high data throughput >> capable distributed DMA architecture under NAVSS >> * Centralized System Controller for Security, Power, and Resource >> Management (DMSC) >> >> See J721E Technical Reference Manual (SPRUIL1, May 2019) >> for further details: http://www.ti.com/lit/pdf/spruil1 >> >> Signed-off-by: Nishanth Menon >> --- >> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 202 ++++++++++++++++++ >> .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 72 +++++++ >> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 176 +++++++++++++++ >> 3 files changed, 450 insertions(+) >> create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi >> create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi >> create mode 100644 arch/arm64/boot/dts/ti/k3-j721e.dtsi >> >> + /* MCUSS_WKUP Range */ >> + <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, >> + <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, >> + <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, >> + <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, >> + <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, >> + <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, >> + <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, >> + <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, >> + <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, >> + <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, >> + <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, >> + <0x00 0x70000000 0x00 0x70000000 0x00 0x00800000>, > > minor nit, can we have this MSMC RAM range line moved to before the > MCUSS_WKUP comment since it doesn't belong to the MCUSS range. Perhaps > can be fixed up while applying the patch. > > Other than that, everything looks good. > > Reviewed-by: Suman Anna Fixed this issue also locally, thanks. -Tero -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel