From: Neil Armstrong <narmstrong@baylibre.com>
To: Hanjie Lin <hanjie.lin@amlogic.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Rob Herring <robh@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Kevin Hilman <khilman@baylibre.com>
Cc: devicetree@vger.kernel.org, Victor Wan <victor.wan@amlogic.com>,
Jianxin Pan <jianxin.pan@amlogic.com>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
linux-usb@vger.kernel.org, Yue Wang <yue.wang@amlogic.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Liang Yang <liang.yang@amlogic.com>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Xingyu Chen <xingyu.chen@amlogic.com>,
Carlo Caione <carlo@caione.org>,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Jian Hu <jian.hu@amlogic.com>
Subject: Re: [PATCH v5 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver
Date: Wed, 15 Jan 2020 09:01:46 +0100 [thread overview]
Message-ID: <69cb2df5-92d0-03a8-aaa8-d9c98909a11e@baylibre.com> (raw)
In-Reply-To: <1578634957-54826-4-git-send-email-hanjie.lin@amlogic.com>
On 10/01/2020 06:42, Hanjie Lin wrote:
> This adds support for the USB2 PHY found in the Amlogic A1 SoC Family.
>
> It supports host mode only.
>
> Signed-off-by: Hanjie Lin <hanjie.lin@amlogic.com>
> Signed-off-by: Yue Wang <yue.wang@amlogic.com>
> ---
> drivers/phy/amlogic/phy-meson-g12a-usb2.c | 85 +++++++++++++++++++++----------
> 1 file changed, 59 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> index 9065ffc..33296f8 100644
> --- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
> @@ -146,11 +146,17 @@
> #define RESET_COMPLETE_TIME 1000
> #define PLL_RESET_COMPLETE_TIME 100
>
> +enum meson_soc_id {
> + MESON_SOC_G12A = 0,
> + MESON_SOC_A1,
> +};
> +
> struct phy_meson_g12a_usb2_priv {
> struct device *dev;
> struct regmap *regmap;
> struct clk *clk;
> struct reset_control *reset;
> + int soc_id;
> };
>
> static const struct regmap_config phy_meson_g12a_usb2_regmap_conf = {
> @@ -164,6 +170,7 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
> {
> struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
> int ret;
> + unsigned int value;
>
> ret = reset_control_reset(priv->reset);
> if (ret)
> @@ -192,18 +199,22 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
> FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) |
> FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9));
>
> - regmap_write(priv->regmap, PHY_CTRL_R18,
> - FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
> - FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
> - PHY_CTRL_R18_MPLL_ACG_RANGE);
> + value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_LK_S, 0x27) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_PFD_GAIN, 1) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_ROU, 7) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_DATA_SEL, 3) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_BIAS_ADJ, 1) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_BB_MODE, 0) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_ALPHA, 3) |
> + FIELD_PREP(PHY_CTRL_R18_MPLL_ADJ_LDO, 1) |
> + PHY_CTRL_R18_MPLL_ACG_RANGE;
> +
> + if (priv->soc_id == MESON_SOC_A1)
> + value |= PHY_CTRL_R18_MPLL_DCO_CLK_SEL;
> +
> + regmap_write(priv->regmap, PHY_CTRL_R18, value);
>
> udelay(PLL_RESET_COMPLETE_TIME);
>
> @@ -227,13 +238,24 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
> FIELD_PREP(PHY_CTRL_R20_USB2_BGR_VREF_4_0, 0) |
> FIELD_PREP(PHY_CTRL_R20_USB2_BGR_DBG_1_0, 0));
>
> - regmap_write(priv->regmap, PHY_CTRL_R4,
> - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
> - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
> - FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
> - PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
> - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
> - FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
> + if (priv->soc_id == MESON_SOC_G12A)
> + regmap_write(priv->regmap, PHY_CTRL_R4,
> + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_7_0, 0xf) |
> + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_15_8, 0xf) |
> + FIELD_PREP(PHY_CTRL_R4_CALIB_CODE_23_16, 0xf) |
> + PHY_CTRL_R4_TEST_BYPASS_MODE_EN |
> + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_1_0, 0) |
> + FIELD_PREP(PHY_CTRL_R4_I_C2L_BIAS_TRIM_3_2, 0));
> + else if (priv->soc_id == MESON_SOC_A1) {
> + regmap_write(priv->regmap, PHY_CTRL_R21,
> + PHY_CTRL_R21_USB2_CAL_ACK_EN |
> + PHY_CTRL_R21_USB2_TX_STRG_PD |
> + FIELD_PREP(PHY_CTRL_R21_USB2_OTG_ACA_TRIM_1_0, 2));
> +
> + /* Analog Settings */
> + regmap_write(priv->regmap, PHY_CTRL_R13,
> + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
> + }
>
> /* Tuning Disconnect Threshold */
> regmap_write(priv->regmap, PHY_CTRL_R3,
> @@ -241,11 +263,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
> FIELD_PREP(PHY_CTRL_R3_HSDIC_REF, 1) |
> FIELD_PREP(PHY_CTRL_R3_DISC_THRESH, 3));
>
> - /* Analog Settings */
> - regmap_write(priv->regmap, PHY_CTRL_R14, 0);
> - regmap_write(priv->regmap, PHY_CTRL_R13,
> - PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
> - FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
> + if (priv->soc_id == MESON_SOC_G12A) {
> + /* Analog Settings */
> + regmap_write(priv->regmap, PHY_CTRL_R14, 0);
> + regmap_write(priv->regmap, PHY_CTRL_R13,
> + PHY_CTRL_R13_UPDATE_PMA_SIGNALS |
> + FIELD_PREP(PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET, 7));
> + }
>
> return 0;
> }
> @@ -286,6 +310,8 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev);
> +
> priv->regmap = devm_regmap_init_mmio(dev, base,
> &phy_meson_g12a_usb2_regmap_conf);
> if (IS_ERR(priv->regmap))
> @@ -321,8 +347,15 @@ static int phy_meson_g12a_usb2_probe(struct platform_device *pdev)
> }
>
> static const struct of_device_id phy_meson_g12a_usb2_of_match[] = {
> - { .compatible = "amlogic,g12a-usb2-phy", },
> - { },
> + {
> + .compatible = "amlogic,g12a-usb2-phy",
> + .data = (void *)MESON_SOC_G12A,
> + },
> + {
> + .compatible = "amlogic,a1-usb2-phy",
> + .data = (void *)MESON_SOC_A1,
> + },
> + { /* Sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, phy_meson_g12a_usb2_of_match);
>
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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next prev parent reply other threads:[~2020-01-15 8:01 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-10 5:42 [PATCH v5 0/6] arm64: meson: Add support for USB on Amlogic A1 Hanjie Lin
2020-01-10 5:42 ` [PATCH v5 1/6] dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings Hanjie Lin
2020-01-11 20:54 ` Martin Blumenstingl
2020-01-13 1:13 ` Hanjie Lin
2020-01-10 5:42 ` [PATCH v5 2/6] dt-bindings: usb: dwc3: Add the Amlogic A1 Family DWC3 Glue Bindings Hanjie Lin
2020-01-11 20:50 ` Martin Blumenstingl
2020-01-13 1:23 ` Hanjie Lin
2020-01-14 20:10 ` Martin Blumenstingl
2020-01-10 5:42 ` [PATCH v5 3/6] phy: amlogic: Add Amlogic A1 USB2 PHY Driver Hanjie Lin
2020-01-11 20:36 ` Martin Blumenstingl
2020-01-15 8:01 ` Neil Armstrong [this message]
2020-01-10 5:42 ` [PATCH v5 4/6] usb: dwc3: Add Amlogic A1 DWC3 glue Hanjie Lin
2020-01-11 20:45 ` Martin Blumenstingl
2020-01-13 1:33 ` Hanjie Lin
2020-01-15 8:01 ` Neil Armstrong
2020-01-16 2:12 ` Hanjie Lin
2020-01-10 5:42 ` [PATCH v5 5/6] arm64: dts: meson: a1: Enable USB2 PHY Hanjie Lin
2020-01-10 5:42 ` [PATCH v5 6/6] arm64: dts: meson: a1: Enable DWC3 controller Hanjie Lin
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