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Fri, 17 Jan 2020 17:57:19 +0100 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D2466100038; Fri, 17 Jan 2020 17:57:13 +0100 (CET) Received: from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C73B222169C; Fri, 17 Jan 2020 17:57:13 +0100 (CET) Received: from lmecxl0912.lme.st.com (10.75.127.47) by SFHDAG3NODE2.st.com (10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 17 Jan 2020 17:57:13 +0100 Subject: Re: [PATCH] ARM: dts: stm32: Add DH Electronics DHCOM SoM and PDK2 board To: Marek Vasut , Patrick DELAUNAY , "linux-arm-kernel@lists.infradead.org" , Maxime Coquelin References: <20200115094714.154581-1-marex@denx.de> <2881f2b053b04d718eba35e61f7b5403@SFHDAG6NODE3.st.com> <435364e8-9737-58ab-1497-f532f57af65d@denx.de> From: Alexandre Torgue Message-ID: <6b3a1cb7-02e9-2293-00c9-710979cbc258@st.com> Date: Fri, 17 Jan 2020 17:57:12 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 In-Reply-To: <435364e8-9737-58ab-1497-f532f57af65d@denx.de> Content-Language: en-US X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG6NODE2.st.com (10.75.127.17) To SFHDAG3NODE2.st.com (10.75.127.8) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-17_04:2020-01-16, 2020-01-17 signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200117_085725_131372_F1CD4A0C X-CRM114-Status: GOOD ( 19.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Patrice CHOTARD , "linux-stm32@st-md-mailman.stormreply.com" Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marek Minor comments below. On 1/17/20 1:51 PM, Marek Vasut wrote: > On 1/15/20 5:46 PM, Patrick DELAUNAY wrote: >> Hi Marek; > > Hi, > >> Adds the Linux Maintainers for STM32M linux patch: > > Added, if there is a need for V2. > > (no further comments below) > > [...] >> >> Hi Alexandre, >> >> Can you review this patch. >> >> Regards >> >> Patrick >> >>> -----Original Message----- >>> From: Marek Vasut >>> Sent: mercredi 15 janvier 2020 10:47 >>> To: linux-arm-kernel@lists.infradead.org >>> Cc: Marek Vasut ; Patrick DELAUNAY >>> ; Patrice CHOTARD >>> Subject: [PATCH] ARM: dts: stm32: Add DH Electronics DHCOM SoM and PDK2 >>> board >>> Importance: High >>> >>> Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier board. >>> This is an SoM with STM32MP157C and an evaluation kit. The baseboard >>> provides Ethernet, UART, USB, CAN and optional display. >>> >>> Signed-off-by: Marek Vasut >>> Cc: Patrick Delaunay >>> Cc: Patrice Chotard >>> --- >>> arch/arm/boot/dts/Makefile | 1 + >>> arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 351 ++++++++++++++++++ >>> arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi | 368 +++++++++++++++++++ >>> 3 files changed, 720 insertions(+) >>> create mode 100644 arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts >>> create mode 100644 arch/arm/boot/dts/stm32mp157c-dhcom-som.dtsi >>> ... >>> + >>> +&m_can1 { >>> + pinctrl-names = "default", "sleep"; >>> + pinctrl-0 = <&m_can1_pins_a>; >>> + pinctrl-1 = <&m_can1_sleep_pins_a>; >>> + status = "okay"; >>> +}; >>> + >>> +&pinctrl { You could define DH pinctrl addons in stm32mp15-pinctrl.dtsi >>> + ethernet0_rmii_pins_a: rmii-0 { >>> + pins1 { >>> + pinmux = , /* >>> ETH1_RMII_TXD0 */ >>> + , /* >>> ETH1_RMII_TXD1 */ >>> + , /* >>> ETH1_RMII_TX_EN */ >>> + , /* >>> ETH1_RMII_REF_CLK */ >>> + , /* ETH1_MDIO >>> */ >>> + ; /* ETH1_MDC >>> */ >>> + bias-disable; >>> + drive-push-pull; >>> + slew-rate = <2>; >>> + }; >>> + pins2 { >>> + pinmux = , /* >>> ETH1_RMII_RXD0 */ >>> + , /* >>> ETH1_RMII_RXD1 */ >>> + ; /* >>> ETH1_RMII_CRS_DV */ >>> + bias-disable; >>> + }; >>> + }; >>> + >>> + ethernet0_rmii_pins_sleep_a: rmii-sleep-0 { >>> + pins1 { >>> + pinmux = , /* >>> ETH1_RMII_TXD0 */ >>> + , /* >>> ETH1_RMII_TXD1 */ >>> + , /* >>> ETH1_RMII_TX_EN */ >>> + , /* >>> ETH1_MDIO */ >>> + , /* >>> ETH1_MDC */ >>> + , /* >>> ETH1_RMII_RXD0 */ >>> + , /* >>> ETH1_RMII_RXD1 */ >>> + , /* >>> ETH1_RMII_REF_CLK */ >>> + ; /* >>> ETH1_RMII_CRS_DV */ >>> + }; >>> + }; >>> + >>> + sai2_pins_a: sai2-0 { >>> + pins1 { >>> + pinmux = , /* >>> SAI2_SD_A */ >>> + , /* >>> SAI2_FS_A */ >>> + ; /* >>> SAI2_SCK_A */ >>> + slew-rate = <0>; >>> + drive-push-pull; >>> + bias-disable; >>> + }; >>> + pins2 { >>> + pinmux = ; /* >>> SAI2_SD_B */ >>> + bias-disable; >>> + }; >>> + }; >>> + >>> + sai2_sleep_pins_a: sai2-sleep-0 { >>> + pins { >>> + pinmux = , /* >>> SAI2_SD_A */ >>> + , /* >>> SAI2_FS_A */ >>> + , /* >>> SAI2_SCK_A */ >>> + ; /* >>> SAI2_SD_B */ >>> + }; >>> + }; >>> + >>> + usart3_pins_a: usart3-0 { >>> + pins1 { >>> + pinmux = ; /* >>> USART3_TX */ >>> + bias-disable; >>> + drive-push-pull; >>> + slew-rate = <0>; >>> + }; >>> + pins2 { >>> + pinmux = ; /* >>> USART3_RX */ >>> + bias-disable; >>> + }; ... >>> +&sdmmc3 { >>> + pinctrl-names = "default", "opendrain", "sleep"; >>> + pinctrl-0 = <&sdmmc3_b4_pins_a>; >>> + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; >>> + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; >>> + broken-cd; >>> + st,neg-edge; >>> + bus-width = <4>; >>> + vmmc-supply = <&v3v3>; >>> + vqmmc-supply = <&v3v3>; >>> + mmc-ddr-3_3v; >>> + status = "okay"; >>> +}; >>> + >>> +&qspi { If you follow alphabetic order reorder this node. >>> + pinctrl-names = "default", "sleep"; >>> + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; >>> + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a >>> &qspi_bk2_sleep_pins_a>; >>> + reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + status = "okay"; >>> + >>> + flash0: mx66l51235l@0 { >>> + compatible = "jedec,spi-nor"; >>> + reg = <0>; >>> + spi-rx-bus-width = <4>; >>> + spi-max-frequency = <108000000>; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + }; >>> +}; >>> + >>> +&uart4 { >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&uart4_pins_a>; >>> + status = "okay"; >>> +}; >>> -- >>> 2.24.1 >> > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel