From: James Morse <james.morse@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
kvm@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 5/5] arm64: Enable and document ARM errata 1319367 and 1319537
Date: Thu, 3 Oct 2019 12:11:00 +0100 [thread overview]
Message-ID: <6d41efac-3606-328a-0a18-f86ed070932c@arm.com> (raw)
In-Reply-To: <20190925111941.88103-6-maz@kernel.org>
Hi Marc,
On 25/09/2019 12:19, Marc Zyngier wrote:
> Now that everything is in place, let's get the ball rolling
> by allowing the corresponding config option to be selected.
> Also add the required information to silicon_arrata.rst.
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 3adcec05b1f6..c50cd4f83bc4 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -523,6 +523,16 @@ config ARM64_ERRATUM_1286807
> invalidated has been observed by other observers. The
> workaround repeats the TLBI+DSB operation.
>
> +config ARM64_ERRATUM_1319367
> + bool "Cortex-A57/A72: Speculative AT instruction using out-of-context translation regime could cause subsequent request to generate an incorrect translation"
> + default y
> + help
> + This option adds work arounds for ARM Cortex-A57 erratum 1319537
> + and A72 erratum 1319367
> +
> + Cortex-A57 and A72 cores could end-up with corrupted TLBs by
> + speculating an AT instruction during a guest context switch.
> +
> If unsure, say Y.
>
> config ARM64_ERRATUM_1463225
>
Nit: You pinched someone elses "If unsure, say Y."!
Thanks,
James
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next prev parent reply other threads:[~2019-10-03 11:11 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-25 11:19 [PATCH 0/5] arm64: KVM: Add workaround for errata 1319367 and 1319537 Marc Zyngier
2019-09-25 11:19 ` [PATCH 1/5] arm64: Add ARM64_WORKAROUND_1319367 for all A57 and A72 versions Marc Zyngier
2019-09-27 8:33 ` Suzuki K Poulose
2019-09-27 9:03 ` Catalin Marinas
2019-09-25 11:19 ` [PATCH 2/5] arm64: KVM: Reorder system register restoration and stage-2 activation Marc Zyngier
2019-09-25 11:19 ` [PATCH 3/5] arm64: KVM: Disable EL1 PTW when invalidating S2 TLBs Marc Zyngier
2019-10-03 11:10 ` James Morse
2019-09-25 11:19 ` [PATCH 4/5] arm64: KVM: Prevent speculative S1 PTW when restoring vcpu context Marc Zyngier
2019-10-03 11:09 ` James Morse
2019-09-25 11:19 ` [PATCH 5/5] arm64: Enable and document ARM errata 1319367 and 1319537 Marc Zyngier
2019-09-27 9:03 ` Catalin Marinas
2019-10-03 11:11 ` James Morse [this message]
2019-10-07 9:31 ` Marc Zyngier
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