From: Jason-JH Lin <jason-jh.lin@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>
Cc: Jassi Brar <jassisinghbrar@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
<chunkuang.hu@kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <hsinyi@chromium.org>,
<nancy.lin@mediatek.com>, <singo.chang@mediatek.com>
Subject: Re: [PATCH v5 2/5] dt-bindings: gce: add gce header file for mt8195
Date: Wed, 25 Aug 2021 15:17:41 +0800 [thread overview]
Message-ID: <72a33d12e45d455ce702f7095d7b290563f3a466.camel@mediatek.com> (raw)
In-Reply-To: <1629800083.22373.4.camel@mtksdaap41>
Hi CK,
Thanks for the review.
On Tue, 2021-08-24 at 18:14 +0800, CK Hu wrote:
> Hi, Jason:
>
> On Wed, 2021-08-18 at 10:40 +0800, jason-jh.lin wrote:
> > To define the subsys id and event id, add gce header file for
> > mt8195.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > include/dt-bindings/gce/mt8195-gce.h | 920
> > +++++++++++++++++++++++++++
> > 1 file changed, 920 insertions(+)
> > create mode 100644 include/dt-bindings/gce/mt8195-gce.h
> >
> > diff --git a/include/dt-bindings/gce/mt8195-gce.h b/include/dt-
> > bindings/gce/mt8195-gce.h
> > new file mode 100644
> > index 000000000000..8c309e59491d
> > --- /dev/null
> > +++ b/include/dt-bindings/gce/mt8195-gce.h
> > @@ -0,0 +1,920 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2018 MediaTek Inc.
> > + *
> > + */
> > +
> > +#ifndef _DT_BINDINGS_GCE_MT8195_H
> > +#define _DT_BINDINGS_GCE_MT8195_H
> > +
> > +/* assign timeout 0 also means default */
> > +#define CMDQ_NO_TIMEOUT 0xffffffff
> > +#define CMDQ_TIMEOUT_DEFAULT 1000
> > +
> > +/* GCE thread priority */
> > +#define CMDQ_THR_PRIO_LOWEST 0
> > +#define CMDQ_THR_PRIO_1 1
> > +#define CMDQ_THR_PRIO_2 2
> > +#define CMDQ_THR_PRIO_3 3
> > +#define CMDQ_THR_PRIO_4 4
> > +#define CMDQ_THR_PRIO_5 5
> > +#define CMDQ_THR_PRIO_6 6
> > +#define CMDQ_THR_PRIO_HIGHEST 7
> > +
> > +/* CPR count in 32bit register */
> > +#define GCE_CPR_COUNT 1312
> > +
> > +/* GCE subsys table */
> > +#define SUBSYS_1400XXXX 0
> > +#define SUBSYS_1401XXXX 1
> > +#define SUBSYS_1402XXXX 2
> > +#define SUBSYS_1c00XXXX 3
> > +#define SUBSYS_1c01XXXX 4
> > +#define SUBSYS_1c02XXXX 5
> > +#define SUBSYS_1c10XXXX 6
> > +#define SUBSYS_1c11XXXX 7
> > +#define SUBSYS_1c12XXXX 8
> > +#define SUBSYS_14f0XXXX 9
> > +#define SUBSYS_14f1XXXX 10
> > +#define SUBSYS_14f2XXXX 11
> > +#define SUBSYS_1800XXXX 12
> > +#define SUBSYS_1801XXXX 13
> > +#define SUBSYS_1802XXXX 14
> > +#define SUBSYS_1803XXXX 15
> > +#define SUBSYS_1032XXXX 16
> > +#define SUBSYS_1033XXXX 17
> > +#define SUBSYS_1600XXXX 18
> > +#define SUBSYS_1601XXXX 19
> > +#define SUBSYS_14e0XXXX 20
> > +#define SUBSYS_1c20XXXX 21
> > +#define SUBSYS_1c30XXXX 22
> > +#define SUBSYS_1c40XXXX 23
> > +#define SUBSYS_1c50XXXX 24
> > +#define SUBSYS_1c60XXXX 25
> > +#define SUBSYS_NO_SUPPORT 99
>
> Why define SUBSYS_NO_SUPPORT?
It is defined as invalid subsys id, but it is not necessary.
I'll remove it.
>
> > +
> > +/* GCE General Purpose Register (GPR) support
> > + * Leave note for scenario usage here
> > + */
> > +/* GCE: write mask */
> > +#define GCE_GPR_R00 0x00
> > +#define GCE_GPR_R01 0x01
> > +/* MDP: P1: JPEG dest */
> > +#define GCE_GPR_R02 0x02
> > +#define GCE_GPR_R03 0x03
> > +/* MDP: PQ color */
> > +#define GCE_GPR_R04 0x04
> > +/* MDP: 2D sharpness */
> > +#define GCE_GPR_R05 0x05
> > +/* DISP: poll esd */
> > +#define GCE_GPR_R06 0x06
> > +#define GCE_GPR_R07 0x07
> > +/* MDP: P4: 2D sharpness dst */
> > +#define GCE_GPR_R08 0x08
> > +#define GCE_GPR_R09 0x09
> > +/* VCU: poll with timeout for GPR timer */
> > +#define GCE_GPR_R10 0x0A
> > +#define GCE_GPR_R11 0x0B
> > +/* CMDQ: debug */
> > +#define GCE_GPR_R12 0x0C
> > +#define GCE_GPR_R13 0x0D
> > +/* CMDQ: P7: debug */
> > +#define GCE_GPR_R14 0x0E
> > +#define GCE_GPR_R15 0x0F
>
> GPR is general purpose register, so do not limit the usage of each
> GPR.
To avoid the same GPR being used by 2 diffenerent client driver at the
same time, we defined the use case that using GPR frequently GPR here
to notify every user.
E.g. MDP use GPR_R10 as temp register whilie VCU is polling the value
in GPR_R10.
But I think we should not limit the usage in the first version, so I'll
remove the scenario here.
>
> > +
>
> [snip]
>
> > +
> > +/* end of hw event */
> > +#define CMDQ_MAX_HW_EVENT 1019
> > +
> > +/* sw token should use the unused event id from 0 to 1023 */
>
> SW token usage could be changed by different software design. So do
> not
> define in binding document.
>
> Regards,
> CK
>
OK, I;ll remove them.
Regards,
Jason-JH.Lin
> > +#define CMDQ_SYNC_TOKEN_INVALID (-1)
> > +
> > +/* Event for imgsys flow control */
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 33
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR 34
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 35
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 36
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_DIP 37
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 38
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 39
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1 41
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2 42
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3 43
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4 44
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5 45
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6 46
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7 47
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8 48
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9 49
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10 50
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11 51
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12 52
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13 53
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14 54
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15 55
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16 56
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17 57
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18 58
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19 59
> > +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20 60
> > +/* Config thread notify trigger thread */
> > +#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 971
> > +/* Trigger thread notify config thread */
> > +#define CMDQ_SYNC_TOKEN_STREAM_EOF 972
> > +/* Block Trigger thread until the ESD check finishes. */
> > +#define CMDQ_SYNC_TOKEN_ESD_EOF 973
> > +#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 974
> > +/* check CABC setup finish */
> > +#define CMDQ_SYNC_TOKEN_CABC_EOF 975
> > +/* Pass-2 notifies VENC frame is ready to be encoded */
> > +#define CMDQ_SYNC_TOKEN_VENC_INPUT_READY 976
> > +/* VENC notifies Pass-2 encode done so next frame may start */
> > +#define CMDQ_SYNC_TOKEN_VENC_EOF 977
> > +
> > +/* Notify normal CMDQ there are some secure task done
> > + * MUST NOT CHANGE, this token sync with secure world
> > + */
> > +#define CMDQ_SYNC_SECURE_THR_EOF 980
> > +#define CMDQ_SYNC_SECURE_THR_EOF_DBG 995
> > +
> > +/* CMDQ use sw token */
> > +#define CMDQ_SYNC_TOKEN_USER_0 981
> > +#define CMDQ_SYNC_TOKEN_USER_1 982
> > +#define CMDQ_SYNC_TOKEN_POLL_MONITOR 983
> > +#define CMDQ_SYNC_TOKEN_TPR_LOCK 984
> > +
> > +/* ISP sw token */
> > +#define CMDQ_SYNC_TOKEN_MSS 985
> > +#define CMDQ_SYNC_TOKEN_MSF 986
> > +
> > +/* GPR access tokens (for register backup)
> > + * There are 15 32-bit GPR, 3 GPR form a set
> > + * (64-bit for address, 32-bit for value)
> > + * MUST NOT CHANGE, these tokens sync with MDP
> > + */
> > +#define CMDQ_SYNC_TOKEN_GPR_SET_0 987
> > +#define CMDQ_SYNC_TOKEN_GPR_SET_1 988
> > +#define CMDQ_SYNC_TOKEN_GPR_SET_2 989
> > +#define CMDQ_SYNC_TOKEN_GPR_SET_3 990
> > +#define CMDQ_SYNC_TOKEN_GPR_SET_4 991
> > +
> > +/* Resource lock event to control resource in GCE thread */
> > +#define CMDQ_SYNC_RESOURCE_WROT0 992
> > +#define CMDQ_SYNC_RESOURCE_WROT1 993
> > +
> > +/* Event for gpr timer, used in sleep and poll with timeout */
> > +#define CMDQ_TOKEN_GPR_TIMER_R0 996
> > +#define CMDQ_TOKEN_GPR_TIMER_R1 997
> > +#define CMDQ_TOKEN_GPR_TIMER_R2 998
> > +#define CMDQ_TOKEN_GPR_TIMER_R3 999
> > +#define CMDQ_TOKEN_GPR_TIMER_R4 1000
> > +#define CMDQ_TOKEN_GPR_TIMER_R5 1001
> > +#define CMDQ_TOKEN_GPR_TIMER_R6 1002
> > +#define CMDQ_TOKEN_GPR_TIMER_R7 1003
> > +#define CMDQ_TOKEN_GPR_TIMER_R8 1004
> > +#define CMDQ_TOKEN_GPR_TIMER_R9 1005
> > +#define CMDQ_TOKEN_GPR_TIMER_R10 1006
> > +#define CMDQ_TOKEN_GPR_TIMER_R11 1007
> > +#define CMDQ_TOKEN_GPR_TIMER_R12 1008
> > +#define CMDQ_TOKEN_GPR_TIMER_R13 1009
> > +#define CMDQ_TOKEN_GPR_TIMER_R14 1010
> > +#define CMDQ_TOKEN_GPR_TIMER_R15 1011
> > +
> > +/* defined in mtk-cmdq-mailbox.h */
> > +/* #define CMDQ_EVENT_MAX 0x3ff
> > */
> > +
> > +#endif
>
>
--
Jason-JH Lin <jason-jh.lin@mediatek.com>
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next prev parent reply other threads:[~2021-08-25 7:19 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-18 2:40 [PATCH v5 0/5] jason-jh.lin
2021-08-18 2:40 ` [PATCH v5 1/5] dt-bindings: mailbox: add definition for mt8195 jason-jh.lin
2021-08-18 2:40 ` [PATCH v5 2/5] dt-bindings: gce: add gce header file " jason-jh.lin
2021-08-24 10:14 ` CK Hu
2021-08-25 7:17 ` Jason-JH Lin [this message]
2021-08-18 2:40 ` [PATCH v5 3/5] arm64: dts: mt8195: add gce node jason-jh.lin
2021-08-18 2:40 ` [PATCH v5 4/5] mailbox: cmdq: add mediatek mailbox support for mt8195 jason-jh.lin
2021-08-18 2:40 ` [PATCH v5 5/5] mailbox: cmdq: add multi-gce clocks " jason-jh.lin
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