From: Matthias Brugger <matthias.bgg@gmail.com>
To: Wenbin Mei <wenbin.mei@mediatek.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org, srv_heupstream@mediatek.com,
linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mediatek@lists.infradead.org,
Chaotian Jing <chaotian.jing@mediatek.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc
Date: Tue, 13 Oct 2020 17:10:46 +0200 [thread overview]
Message-ID: <72ae1d89-fe31-4f50-15c0-29119d662ea1@gmail.com> (raw)
In-Reply-To: <20201012124547.16649-5-wenbin.mei@mediatek.com>
On 12/10/2020 14:45, Wenbin Mei wrote:
> MT8192 msdc is an independent sub system, we need control more bus
> clocks for it.
> Add support for the additional subsys clocks to allow it to be
> configured appropriately.
>
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> ---
> drivers/mmc/host/mtk-sd.c | 74 +++++++++++++++++++++++++++++----------
> 1 file changed, 56 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index a704745e5882..c7df7510f120 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
[...]
> +static int msdc_of_clock_parse(struct platform_device *pdev,
> + struct msdc_host *host)
> +{
> + int ret;
> +
> + host->src_clk = devm_clk_get(&pdev->dev, "source");
> + if (IS_ERR(host->src_clk))
> + return PTR_ERR(host->src_clk);
> +
> + host->h_clk = devm_clk_get(&pdev->dev, "hclk");
> + if (IS_ERR(host->h_clk))
> + return PTR_ERR(host->h_clk);
> +
> + host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
> + if (IS_ERR(host->bus_clk))
> + host->bus_clk = NULL;
> +
> + /*source clock control gate is optional clock*/
> + host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
> + if (IS_ERR(host->src_clk_cg))
> + host->src_clk_cg = NULL;
> +
> + host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg");
> + if (IS_ERR(host->sys_clk_cg))
> + host->sys_clk_cg = NULL;
> +
> + /* If present, always enable for this clock gate */
> + clk_prepare_enable(host->sys_clk_cg);
> +
> + host->bulk_clks[0].id = "pclk_cg";
> + host->bulk_clks[1].id = "axi_cg";
> + host->bulk_clks[2].id = "ahb_cg";
That looks at least suspicious. The pointers of id point to some strings defined
in the function. Aren't they out of scope once msdc_of_clock_parse() has returned?
Regards,
Matthias
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next prev parent reply other threads:[~2020-10-13 15:12 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-12 12:45 [PATCH v6 0/4] Add mmc support for MT8192 SoC Wenbin Mei
2020-10-12 12:45 ` [PATCH v6 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema Wenbin Mei
2020-10-13 16:55 ` Rob Herring
2020-10-12 12:45 ` [PATCH v6 2/4] mmc: dt-bindings: add support for MT8192 SoC Wenbin Mei
2020-10-13 16:57 ` Rob Herring
2020-10-12 12:45 ` [PATCH v6 3/4] arm64: dts: mt8192: add mmc device node Wenbin Mei
2020-10-12 12:45 ` [PATCH v6 4/4] mmc: mediatek: Add subsys clock control for MT8192 msdc Wenbin Mei
2020-10-13 9:59 ` Nicolas Boichat
2020-10-13 15:10 ` Matthias Brugger [this message]
2020-10-14 2:28 ` Wenbin Mei
2020-10-14 3:06 ` Nicolas Boichat
2020-10-14 7:44 ` Matthias Brugger
2020-10-14 8:01 ` Nicolas Boichat
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