From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29863C4727F for ; Wed, 30 Sep 2020 10:29:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C61052074A for ; Wed, 30 Sep 2020 10:29:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="PSK5ktdn" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C61052074A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=6q/cMyREbl1OzJxZB2ss6ETkizPXe0e73HGQmoB+9WM=; b=PSK5ktdnZ2K+dnVsXVe9O0Yrh E8Mpval+M6v3NTZ9M36H1vfrL1v5fBGRJVhprXRfiHFMVykkS9hGUJepD1t+bOJzgCUNCPqjCKZ0R OGKwyEi4DqdY3iB2Ip1I45MnC5qNdqCV0YJt+RBUAapaDzjC4uB7FNbtschQQXrfeHxntxlXMjqlD D+7Yw0/ZWu+ueHzYBXr6AxvA9afGms83igSLN0aNGwLQ/LW/AzXQFLF7fLSN1cH6hVwBg/eWzi9NK QYTh/OX2lWHFzp5S8BMcUjNUEP7+ynJ21ObC9Fo98uvu2S9JldrVAe9M7CVjjN3VxVc/5sTMb30gL jHQ5or/Fg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kNZL2-0007S4-Oz; Wed, 30 Sep 2020 10:27:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kNZL0-0007Qs-TV for linux-arm-kernel@lists.infradead.org; Wed, 30 Sep 2020 10:27:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F2527D6E; Wed, 30 Sep 2020 03:27:52 -0700 (PDT) Received: from [10.57.49.167] (unknown [10.57.49.167]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B1B5A3F70D; Wed, 30 Sep 2020 03:27:51 -0700 (PDT) Subject: Re: [PATCH 12/19] coresight: etm4x: Cleanup secure exception level masks To: mike.leach@linaro.org References: <20200911084119.1080694-1-suzuki.poulose@arm.com> <20200911084119.1080694-13-suzuki.poulose@arm.com> <22c9fccf-6d87-5d9f-465f-0ef487984f0d@arm.com> From: Suzuki K Poulose Message-ID: <72dd83d2-462a-c68b-290f-533d17a1e8fa@arm.com> Date: Wed, 30 Sep 2020 11:32:25 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200930_062755_042549_7EEC49C3 X-CRM114-Status: GOOD ( 27.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, anshuman.khandual@arm.com, mathieu.poirier@linaro.org, linux-arm-kernel@lists.infradead.org, leo.yan@linaro.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mike, On 09/22/2020 01:47 PM, Mike Leach wrote: > Hi Suzuki, > >>>> @@ -935,16 +935,9 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config) >>>> static u64 etm4_get_access_type(struct etmv4_config *config) >>>> { >>>> u64 access_type = etm4_get_ns_access_type(config); >>>> - u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0; >>>> >>>> - /* >>>> - * EXLEVEL_S, bits[11:8], don't trace anything happening >>>> - * in secure state. >>>> - */ >>>> - access_type |= (ETM_EXLEVEL_S_APP | >>>> - ETM_EXLEVEL_S_OS | >>>> - s_hyp | >>>> - ETM_EXLEVEL_S_MON); >>>> + /* All supported secure ELs are excluded */ >>>> + access_type |= (u64)config->s_ex_level << TRCACATR_EXLEVEL_SHIFT; >>>> >>> >>> What is the << TRCACATR_EXLEVEL_SHIFT doing here? >> >> The config->s_ex_level is the EXLVEL mask from the TRCIDR3 shifted to bit 0, as above. >> We need to make sure that we use the mask in the correct position for TRCACATR register. >> Basically, we simply exclude all the secure levels supported by the ETM. >> > > Sorry, should have been a little more explicit. This breaks the next patch! > >>> >>>> return access_type; >>>> } >>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >>>> index efd903688edd..407ad6647f36 100644 >>>> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >>>> @@ -522,6 +522,8 @@ >>>> /* PowerDown Control Register bits */ >>>> #define TRCPDCR_PU BIT(3) >>>> >>>> +#define TRCACATR_EXLEVEL_SHIFT 8 >>>> + >>>> /* secure state access levels - TRCACATRn */ >>>> #define ETM_EXLEVEL_S_APP BIT(8) >>>> #define ETM_EXLEVEL_S_OS BIT(9) >>>> @@ -604,7 +606,7 @@ >>>> * @vmid_mask0: VM ID comparator mask for comparator 0-3. >>>> * @vmid_mask1: VM ID comparator mask for comparator 4-7. >>>> * @ext_inp: External input selection. >>>> - * @arch: ETM architecture version (for arch dependent config). >>>> + * @s_ex_level: Secure ELs where tracing is supported. >>>> */ >>>> struct etmv4_config { >>>> u32 mode; >>>> @@ -648,7 +650,7 @@ struct etmv4_config { >>>> u32 vmid_mask0; >>>> u32 vmid_mask1; >>>> u32 ext_inp; >>>> - u8 arch; >>>> + u8 s_ex_level; >>>> }; >>>> >>>> /** >>>> -- >>>> 2.24.1 >>>> >>> >>> Perhaps this patch could be combined with the next patch as it >>> operates on the same set of flags. >>> >> >> I agree that they both deal with the same set of masks. However, functionally >> they have separate purposes. >> >> 1) This patch disconnects the usage of drvdata->arch field to determine >> the secure exception level mask. This is more of a correctness, as a given >> v4.4 implementation may not have a Secure EL2. >> >> 2) The next patch cleans up the way we define and use all the exception level >> masks, both secure and non-secure. >> > > > > Applying this and the next patch which moves to the bits being indexed > from 0 for a common reusable field gets you the following code > sequence:- Good catch. > > static u64 etm4_get_ns_access_type(struct etmv4_config *config) > { > u64 access_type = 0; > > /* > * EXLEVEL_NS, bits[15:12] > * The Exception levels are: > * Bit[12] Exception level 0 - Application > * Bit[13] Exception level 1 - OS > * Bit[14] Exception level 2 - Hypervisor > * Bit[15] Never implemented > */ > Updated the comments. > > [ MJL: at this point the comment is true to an extent but no longer > applies to the values #defines below - which have been shifted by the > change to the #defines to form a field that is indexed from bit 0] > > > static u64 etm4_get_access_type(struct etmv4_config *config) > { > u64 access_type = etm4_get_ns_access_type(config); > > /* All supported secure ELs are excluded */ > access_type |= (u64)config->s_ex_level << TRCACATR_EXLEVEL_SHIFT; > > [MJL: Now we are OR ing a 0 bit index based field (NS access type) > with another 0 index based field - but shifting it for some reason?] That was a mistake. I will drop this shift from here to make get_access_type() and this should work. Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel