From: Marc Zyngier <maz@kernel.org>
To: ito-yuichi@fujitsu.com
Cc: sumit.garg@linaro.org, jason@lakedaemon.net,
catalin.marinas@arm.com, linux-kernel@vger.kernel.org,
tglx@linutronix.de, will@kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/2] Enable support IPI_CPU_CRASH_STOP to be pseudo-NMI
Date: Tue, 29 Sep 2020 11:54:49 +0100 [thread overview]
Message-ID: <74f6c812041970cb8f5e8c0da22fca92@kernel.org> (raw)
In-Reply-To: <OSAPR01MB4227204DB45A285761B520998F320@OSAPR01MB4227.jpnprd01.prod.outlook.com>
On 2020-09-29 06:50, ito-yuichi@fujitsu.com wrote:
> Hi Marc
[...]
>> >> The patch has been tested on ThunderX.
>>
>> Which ThunderX? TX2 (at least the incarnation I used in the past)
>> wasn't able
>> to correctly deal with priorities.
>
> I tried it with ThunderX CN8890.
> If you tell me steps to reproduce the problem of TX2, I will
> investigate it with TX as well.
PMR_EL1 reporting fantasy values, non-uniform priority support across
the interrupt classes, and generally prone to lockups. The original TX
is a very different machine though (TX 1 and 2 only share the engraving
of the manufacturer on the heat-spreader).
M.
--
Jazz is not dead. It just smells funny...
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next prev parent reply other threads:[~2020-09-29 10:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-24 4:42 [PATCH 0/2] Enable support IPI_CPU_CRASH_STOP to be pseudo-NMI Yuichi Ito
2020-09-24 4:42 ` [PATCH 1/2] irqchip/gic-v3: Enable support for SGIs to act as NMIs Yuichi Ito
2020-09-24 4:42 ` [PATCH 2/2] Register IPI_CPU_CRASH_STOP IPI as pseudo-NMI Yuichi Ito
2020-09-28 2:43 ` [PATCH 0/2] Enable support IPI_CPU_CRASH_STOP to be pseudo-NMI ito-yuichi
2020-09-28 8:59 ` Marc Zyngier
2020-09-29 5:50 ` ito-yuichi
2020-09-29 10:54 ` Marc Zyngier [this message]
2020-09-30 8:51 ` ito-yuichi
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