Re: [PATCH net-next 1/3] arm64: barrier: add DGH macros to control memory accesses merging

From: "huangguangbin (A)" <huangguangbin2@huawei.com>
To: Mark Rutland <mark.rutland@arm.com>, Will Deacon <will@kernel.org>
Cc: <davem@davemloft.net>, <kuba@kernel.org>,
	<catalin.marinas@arm.com>, <maz@kernel.org>,
	<dbrazdil@google.com>, <qperret@google.com>,
	<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <lipeng321@huawei.com>,
	<peterz@infradead.org>
Subject: Re: [PATCH net-next 1/3] arm64: barrier: add DGH macros to control memory accesses merging
Date: Thu, 24 Jun 2021 22:18:03 +0800	[thread overview]
Message-ID: <7561019b-f8e6-2191-5aba-3464f06be537@huawei.com> (raw)
In-Reply-To: <20210622123221.GA71782@C02TD0UTHF1T.local>


On 2021/6/22 20:32, Mark Rutland wrote:
> On Tue, Jun 22, 2021 at 01:16:31PM +0100, Will Deacon wrote:
>> On Tue, Jun 22, 2021 at 07:11:09PM +0800, Guangbin Huang wrote:
>>> From: Xiongfeng Wang <wangxiongfeng2@huawei.com>
>>>
>>> DGH prohibits merging memory accesses with Normal-NC or Device-GRE
>>> attributes before the hint instruction with any memory accesses
>>> appearing after the hint instruction. Provide macros to expose it to the
>>> arch code.
>>
>> Hmm.
>>
>> The architecture states:
>>
>>    | DGH is a hint instruction. A DGH instruction is not expected to be
>>    | performance optimal to merge memory accesses with Normal Non-cacheable
>>    | or Device-GRE attributes appearing in program order before the hint
>>    | instruction with any memory accesses appearing after the hint instruction
>>    | into a single memory transaction on an interconnect.
>>
>> which doesn't make a whole lot of sense to me, in all honesty.
> 
> I think there are some missing words, and this was supposed to say
> something like:
> 
> | DGH is a hint instruction. A DGH instruction *indicates that it* is
> | not expected to be performance optimal to merge memory accesses with
> | Normal Non-cacheable or Device-GRE attributes appearing in program
> | order before the hint instruction with any memory accesses appearing
> | after the hint instruction into a single memory transaction on an
> | interconnect.
> 
> ... i.e. it's a hint to the CPU to avoid merging accesses which are
> either side of the DGH, so that the prior accesses don't get
> indefinitely delayed waiting to be merged.
> 
> I'll try to get the documentation fixed, since as-is the wording does
> not make sense.
> 
> Thanks,
> Mark.
> .
> 
Thanks very much, we will fix the documentation.

Thanks,
Guangbin,
.


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