Re: [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings

[Matthias Brugger <matthias.bgg@gmail.com>]

On 01/07/2020 10:38, EastL wrote:
> On Fri, 2020-06-19 at 11:36 +0200, Matthias Brugger wrote:
>>
>> On 19/06/2020 10:04, EastL wrote:
>>> Document the devicetree bindings for MediaTek Command-Queue DMA controller
>>> which could be found on MT6779 SoC or other similar Mediatek SoCs.
>>>
>>> Signed-off-by: EastL <EastL.Lee@mediatek.com>
>>
>> Still missing the full name.
> 
> Sorry I thought it was only needed in the yaml file
> I will fix in next version.\

Just to make sure there is no missunderstanding, I mean your git settings. Your
Signed-off-by should look like:

EastL Lee <EastL.Lee@mediatek.com>

Regards,
Matthias

>>
>>> ---
>>>  .../devicetree/bindings/dma/mtk-cqdma.yaml         | 114 +++++++++++++++++++++
>>>  1 file changed, 114 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
>>> new file mode 100644
>>> index 0000000..e6fdf05
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
>>> @@ -0,0 +1,114 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>
>> You missed the brackets ().
> OK
>>
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: MediaTek Command-Queue DMA controller Device Tree Binding
>>> +
>>> +maintainers:
>>> +  - EastL Lee <EastL.Lee@mediatek.com>
>>> +
>>> +description:
>>> +  MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
>>> +  is dedicated to memory-to-memory transfer through queue based
>>> +  descriptor management.
>>> +
>>> +allOf:
>>> +  - $ref: "dma-controller.yaml#"
>>> +
>>> +properties:
>>> +  "#dma-cells":
>>> +    minimum: 1
>>> +    maximum: 255
>>> +    description:
>>> +      Used to provide DMA controller specific information.
>>> +
>>> +  compatible:
>>> +    oneOf:
>>> +      - const: mediatek,common-cqdma
>>
>> What is the common-cqdma for if we have only one compatible specifying the SoC.
>> Actually I'm not a great fan of the common-cqdma thing. I'd prefer a fallback
>> compatible that has the name of the first SoC implementing the same device.
>>
>> Regards,
>> Matthias
>>
> OK, I'll remove common compatible.
> 
>>> +      - const: mediatek,mt6765-cqdma
>>> +      - const: mediatek,mt6779-cqdma
>>> +
>>> +  reg:
>>> +    minItems: 1
>>> +    maxItems: 5
>>> +    description:
>>> +        A base address of MediaTek Command-Queue DMA controller,
>>> +        a channel will have a set of base address.
>>> +
>>> +  interrupts:
>>> +    minItems: 1
>>> +    maxItems: 5
>>> +    description:
>>> +        A interrupt number of MediaTek Command-Queue DMA controller,
>>> +        one interrupt number per dma-channels.
>>> +
>>> +  clocks:
>>> +    maxItems: 1
>>> +
>>> +  clock-names:
>>> +    const: cqdma
>>> +
>>> +  dma-channel-mask:
>>> +    $ref: /schemas/types.yaml#definitions/uint32
>>> +    description:
>>> +       For DMA capability, We will know the addressing capability of
>>> +       MediaTek Command-Queue DMA controller through dma-channel-mask.
>>> +    items:
>>> +      minItems: 1
>>> +      maxItems: 63
>>> +
>>> +  dma-channels:
>>> +    $ref: /schemas/types.yaml#definitions/uint32
>>> +    description:
>>> +      Number of DMA channels supported by MediaTek Command-Queue DMA
>>> +      controller, support up to five.
>>> +    items:
>>> +      minItems: 1
>>> +      maxItems: 5
>>> +
>>> +  dma-requests:
>>> +    $ref: /schemas/types.yaml#definitions/uint32
>>> +    description:
>>> +      Number of DMA request (virtual channel) supported by MediaTek
>>> +      Command-Queue DMA controller, support up to 32.
>>> +    items:
>>> +      minItems: 1
>>> +      maxItems: 32
>>> +
>>> +required:
>>> +  - "#dma-cells"
>>> +  - compatible
>>> +  - reg
>>> +  - interrupts
>>> +  - clocks
>>> +  - clock-names
>>> +  - dma-channel-mask
>>> +  - dma-channels
>>> +  - dma-requests
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> +  - |
>>> +    #include <dt-bindings/interrupt-controller/irq.h>
>>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +    #include <dt-bindings/clock/mt6779-clk.h>
>>> +    cqdma: dma-controller@10212000 {
>>> +        compatible = "mediatek,mt6779-cqdma";
>>> +        reg = <0x10212000 0x80>,
>>> +            <0x10212080 0x80>,
>>> +            <0x10212100 0x80>;
>>> +        interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
>>> +            <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
>>> +            <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
>>> +        clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
>>> +        clock-names = "cqdma";
>>> +        dma-channel-mask = <63>;
>>> +        dma-channels = <3>;
>>> +        dma-requests = <32>;
>>> +        #dma-cells = <1>;
>>> +    };
>>> +
>>> +...
>>>
> 

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